System-on-Chip.Test.Architectures.pdf

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'System-on-Chip.Test.Architectures.pdf'
SYSTEM-ON-CHIP TESTARCHITECTURES The Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology The Designer’ s Guide to VHDL, Second Edition Peter J. Ashenden The System Designer’ s Guide to VHDL-AMS Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden Modeling Embedded Systems and SoCs Axel Jantsch ASIC and FPGA Verification: A Guide to Component Modeling Richard Munden Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne Wolf Functional Verification Bruce Wile, John Goss, and Wolfgang Roesner Customizable and Configurable Embedded Processors Edited by Paolo Ienne and Rainer Leupers Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles however, we give an overview of some of these promising techniques in many of the chap- ters. Memory testing as well as the Institute of Electrical and Electronics Engineers (IEEE) boundary scan and core-based test standards used in SOC testing (including 1149.1, 1149.4, 1149.6, and 1500) were covered extensively in the first book and, as a result, are not repeated in this book; instead the reader is referred to the first book and its associated references for details on these topics. It should be noted, however, that new material related to these topics is included in a number of chapters in this book. The advanced topics covered in this book can also be categorized into mul- tiple sections, with each section consisting of multiple chapters. They are as follows: 1.DFT Architectures for Digital Logic Testing (Chapter 2) System/Network-on-Chip Testing (Chapter 4) System-in-Package Testing (Chapter 5) FPGA Testing (Chapter 12) High-Speed I/O Interfaces (Chapter 14) Analog and Mixed-Signal Testing (Chapter 15) 2.New Fault Models and Advanced Techniques for Delay Testing (Chapter 6) Low-Power Testing (Chapter 7) Coping with Physical Failures, Soft Errors, and Reliability Issues (Chapter 8) Software-Based Self-Testing (Chapter 11) RF Testing (Chapter 16) 3.Yield and Reliability Enhancement Fault-Tolerant Design (Chapter 3) Design for Manufacturability and Yield (Chapter 9) Design for Debug and Diagnosis (Chapter 10) xxivPreface 4.Nanotechnology Testing Aspects MEMS Testing (Chapter 13) ResonantTunnelingDiodes,Quantum-DotCellularAutomata,Hybrid CMOS/Nanowires/Nanodevices, and Carbon Nanotubes (Chapter 17) Each chapter of this book follows a specific format. The subject matter of the chapter is first introduced, with a historical perspective provided, if applicable. Related methods are explained in detail next. Then, industry practices, if applica- ble, are described before concluding remarks. Each chapter (except Chapter 17) contains a variety of exercises to allow this book to be used as a textbook for an advanced course in testing. Every chapter concludes with acknowledgment to contributors and reviewers and a list of references. Chapter 1 introduces system-on-chip (SOC) testing. It begins with a discussion of the importance of testing as a requisite for achieving manufacturing quality and then identifies test challenges of the nanometer design era. This is followed by a brief overview of some of the IEEE boundary scan and core-based test standards that are widely used within industry (including 1149.1, 1149.4, 1149.6, and 1500). SOC examples practiced in industry are shown to illustrate the test challenges we face today. Chapter 2 provides an overview of the most important test architectures for digital logic testing. Three basic design-for-testability (DFT) techniques widely used in industry are covered first: scan design, logic built-in self-test (BIST), and test compression. For each DFT technique, fundamental and advanced test architectures suitable for low-power and at-speed applications are discussed. The remainder of the chapter is devoted to random-access scan, a promising alternative to scan design for test power reduction. Chapter 3 covers fault-tolerant design techniques that are applicable to both SOC designs and system applications. As the topic is quite broad, care is taken to describe widely used coding methods and fault tolerance schemes in an easy-to-grasp man- ner with extensive illustrations and examples. The chapter lists applications where the discussed techniques can be utilized. Chapter 4 is devoted to both system-on-chip (SOC) and network-on-chip (NOC) test architectures. Various techniques for test access and test scheduling are thoroughly examined and presented. The chapter includes a discussion of the similarities and differences between the two as well as examples of each. Industrial designs are studied to show how these techniques are applicable to SOC and NOC testing. Chapter 5 describes important test cost and product quality aspects of pack- ing multiple dies in a system-in-package (SIP). After an introduction to the basic technologies, specific test challenges are presented. A number of bare-die test tech- niques to find known-good-dies are subsequently described. Functional system test and embedded component test techniques are then presented to test the SIP at the system level. The chapter ends with a brief discussion of future SIP design and test challenges related to nanometer technologies. Chapter 6 addresses the testing of delay faults. The main focus of this chapter is on testing defect-based delay faults, often called small delay defect testing. Without Prefacexxv loss of generality, however, conventional yet efficient delay fault simulation and test generation techniques for transition, gate-delay, and path-delay faults are first described. Advanced fault simulation and test pattern generation techniques asso- ciated with defect-based delay faults are then explained in detail. Chapter 7 is devoted to low-power testing. After providing the motivations for reducing power during testing, power modeling and terminology used in the chapter are given. The main issues of excessive test power are then described. The remain- der of the chapter is devoted to providing an overview of structural and algorithmic solutions that can be used to alleviate the issues raised by excessive power con- sumption during test application for digital nanometer designs. Chapter 8 covers the full spectrum of defect-based test methods to cope with physical failures, soft errors, and reliability issues. First, new fault models are devel- oped and solutions are presented to deal with noise-induced signal integrity issues. Defect-based tests are then discussed to further screen new defect-induced manu- facturing faults. Finally, the rest of the chapter is devoted to illustrating adaptive designs and error-resilient architectures to tolerate soft errors and manufacturing faults. Chapter 9 delves into the emerging hot topics of design for manufacturability (DFM) and design for yield (DFY). The chapter first describes in detail how lithog- raphy and variability during the manufacturing process can affect yield and induce defects. Then, innovative DFM and DFY techniques to improve yield and reduce defect level are explained in detail. Chapter 10 is devoted to silicon debug and diagnosis, with heavy emphasis on design-for-debug architectures at the logic, circuit, and layout levels. This is com- plemented by an overview of common probing and diagnosis technologies for both wirebond and flip-chip packaging. The chapter also touches on system-level debug so as to link system issues back to silicon implementations. Finally, some of the future challenges unique to debug and diagnosis are also presented. Chapter 11 provides a comprehensive discussion of software-based self-testing. The idea is to use on-chip programmable resources such as embedded processors to perform self-test and self-diagnosis. After explaining the basic concepts, var- ious software-based self-test techniques are described to target processor cores, global interconnects, nonprogrammable cores, and analog and mixed-signal (AMS) circuits. Self-diagnosis techniques are also covered. Chapter 12 addresses testing field programmable gate arrays (FPGAs) beginning with an overview of general FPGA architectures and operation. Following a dis- cussion of the test challenges associated with FPGAs, various test approaches for FPGAs are described. The remainder of the chapter focuses on BIST and diagno- sis of the programmable logic and routing resources in FPGAs. The chapter also presents new techniques for testing specialized cores such as configurable mem- ories as well as new directions in FPGA testing using embedded processor-based on-chip reconfiguration. Chapter 13 covers the testing of microelectromechanical systems (MEMS) devices that present new and interesting challenges as compared to the testing of micro- electronics. This is partially because MEMS devices are designed to physically interact with the environment in which they operate. MEMS testing considerations, xxviPreface methods, and examples are presented, along with DFT and BIST techniques that have been proposed and implemented in commercially available MEMS devices. Chapter 14 is devoted to high-speed parallel/serial I/O link testing at both component and system levels. This chapter starts with a discussion on signaling properties, such as jitter, noise, and bit error rate (BER), which impact the choice of high-speed I/O architectures. At the component level, instrumentation-based test methods for I/O characterization and DFT-assisted test methods for manufactur- ing test are first explained in detail. Novel DFT approaches for testing emerging circuits at signaling rates over 1 GHz, such as equalization and compensation, are also covered. At the system level, interconnect test methods using the IEEE 1149.1 and 1149.6 standards as well as the interconnect BIST (IBIST) method are then included. Chapter 15 addresses testing analog and mixed-signal (AMS) circuits that are more frequently being incorporated in an SOC. The first book presented many of the basic issues and techniques for testing AMS circuits along with examples of testing discrete analog circuits. Although some of these basics are repeated in this book, this chapter focuses on mixed-signal BIST architectures that can be included in SOC implementations to test the analog cores and modules. Chapter 16 extends AMS testing concepts to issues and techniques associated with testing radiofrequency (RF) circuits. This chapter outlines key test specifications for RF circuits and systems as well as covers industry practices for such devices. In addition, this chapter explains the operating principles of various test instru- mentations widely used for AMS and RF testing and describes general automatic test equipment (ATE) architecture. From a production test perspective, concepts related to accuracy and repeatability are also discussed. Chapter 17 is devoted to test technology trends for emerging nanotechnolo- gies that are beyond the conventional CMOS. It introduces novel devices, circuits, architectures, and systems that have been proposed as alternatives to the CMOS at nanoscale dimensions, such as resonant tunneling diodes (RTDs), quantum- dot cellular automata (QCA), silicon nanowires, single electron transistors, and carbon nanotubes(CNTs). Defect characterization, fault modeling, test generation techniques, and the built-in self-test of systems built using such nanodevices, par- ticularly for RTDs, QCA, and crossbar arrays, are discussed. Defect tolerance tech- niques for carbon nanotube field effect transistors (CNFETs) are also covered. IN THECLASSROOM This book is designed to be used as an advanced text for seniors and graduate students in computer engineering, computer science, and electrical engineering. It is also intended for use as a reference book for researchers and practitioners. The book is self-contained with most topics covered extensively from fundamental concepts to the current techniques used in research and industry. However, we assume that students have had basic courses in logic design, computer science, probability theory, and the fundamental testing and DFT techniques. Attempts are made to present algorithms, where possible, in an easily understood format. To encourage self-learning, the instructor or reader is advised to check the Elsevier companion Web site (www.books.elsevier.com/companions) to access up-to-date software and lecture slides. Instructors will have additional privileges to access the Solutions directory for all exercises given in each chapter by visiting www.textbooks.elsevier.com and registering a username and password. Laung-Terng (L.-T.) Wang Charles E. Stroud Nur A. Touba This page intentionally left blank ACKNOWLEDGMENTS The editors would like to acknowledge many of their colleagues who helped create this book. Foremost are the 39 chapter/section contributors listed here. Without their strong commitments to contributing the chapters and sections of their spe- cialty to the book in a timely manner, it would not have been possible to publish this book. We also would like to thank the external contributors and reviewers for providing invaluable materials and feedback to improve the contents of this book. We wish to thank Alexandre de Morais Amory (UFRGS, Porto Alegre, Brazil), Dr. Jean-Marie Brunet (Mentor Graphics, Wilsonville, OR), Prof. Erika Cota (UFRGS, Brazil), C. Grecu (University of British Columbia, Canada), Dr. Vikram Iyengar (IBM, Burlington, VT), Dr. Ming Li (Siemens, Shanghai, China), Ke Li (University of Cincinnati), Dr. Lars Liebmann (IBM, Yorktown Heights, NY), Erik Jan Marinissen (NXP Semiconductors, Eindhoven, The Netherlands), Prof. David Pan (Univer- sity of Texas, Austin, TX), Dr. Anuja Sehgal (AMD, Sunnyvale, CA), Jing Wang (Texas A copyeditor Karen Carriere; senior production editor Dawnmarie Simpson; and associate editor Michele Cronin. Finally, we would like to acknowledge the generosity of SynTest Technologies (Sunnyvale, CA) for allowing Elsevier to put an exclusive version of the company’ s most recent VLSI testing and DFT software on the Elsevier companion Web site (www.books.elsevier.com/companions) for readers to use in conjunction with the book to become acquainted with DFT practices. CONTRIBUTORS Robert C. Aitken, R Chair, IEEE 1149.6 Standard Committee John (Marty) Emmert, Associate Professor (Chapter 15) Department of Electrical Engineering, Wright State University, Dayton, Ohio Patrick Girard, CNRS Research Director (Chapter 7) LIRMM/CNRS, Montpellier, France Pallav Gupta, Assistant Professor (Chapter 17) Department of Electrical and Computer Engineering, Villanova University, Villanova, Pennsylvania Michael S. Hsiao, Professor and Dean’ s Faculty Fellow (Chapter 6) Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacks- burg, Virginia Jiun-Lang Huang, Assistant Professor (Chapter 11) Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Ta
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