vhdl程序设计数字电子表

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1、第六章VHDL综合应用数字电子时钟显示电路6个七段数码管SEGOUT(8)CLR时钟显示电路方框图CPFPGASELOUT(6)24进制计数器60进制计数器60进制计数器BCD七段译码电路BCD选择BCD(8)BIN(6)6个七段数码管扫描电路S(3)SEG(8)NUM(4)BCD(3-0)BCD(7-4)ENB(0)ENB(1)ENB(2)DBHDBMDBSBIN(6)时钟显示电路方框图SECCLRCYHCYSCYM分频器QCP38译码24进制计数器60进制计数器60进制计数器BCD七段译码电路BCD选择BCD(8)BIN(6)6个七段数码管扫描电路S(3)SEG(8)NU

2、M(4)BCD(3-0)BCD(7-4)ENB(0)ENB(1)ENB(2)DBHDBMDBSBIN(6)时钟显示电路方框图SECCLRCYHCYSCYM分频器QCP38译码PROCESS(CP)BeginIFCP'EventANDCP='1'thenDLY<=Q(21);Q<=Q+1;ENDIF;ENDPROCESS;Free_Counter:BlockSignalQ:STD_LOGIC_VECTOR(24DOWNTO0);SignalDLY:STD_LOGIC;BeginPROCESS(CP)BeginIFCP'EventANDCP='1'thenDLY<=Q(21);Q<=Q+

3、1;ENDIF;ENDPROCESS;SEC<=Q(21)ANDNOTDLY;--about1HzS<=Q(15DOWNTO13);--about250HzENB<="001"WHEN(S=0ORS=1)ELSE"010"WHEN(S=2ORS=3)ELSE"100"WHEN(S=4ORS=5)ELSE"000";BIN<=DBSWHENENB="001"ELSEDBMWHENENB="010"ELSEDBHWHENENB="100"ELSE"000000";EndBlockFree_Counter;--主文件声明代码COMPONENTCOUNTER60PORT(CP:INSTD_L

4、OGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY60:OUTSTD_LOGIC);ENDCOMPONENT;--子文件定义代码--***************************************************LIBRARYIEEE;USEIEEE.STD_LOGIC_UNSIGNED.ALL;--***************************************************ENTITYCOUNTER60ISPORT

5、(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY60:OUTSTD_LOGIC);ENDCOUNTER60;--子文件定义代码ARCHITECTUREaOFCOUNTER60ISSIGNALQ:STD_LOGIC_VECTOR(5DOWNTO0);SIGNALRST,DLY:STD_LOGIC;BEGINPROCESS(CP,RST)BEGINIFRST='1'THENQ<="000000";ELSIFCP'eventANDCP='1'TH

6、ENDLY<=Q(5);IFEC='1'THENQ<=Q+1;ENDIF;ENDIF;ENDPROCESS;CY60<=NOTQ(5)ANDDLY;RST<='1'WHENQ=60ORCLR='1'ELSE'0';BIN<=QWHENS='1'ELSE"000000";ENDa;--主文件声明代码COMPONENTCOUNTER24PORT(CP:INSTD_LOGIC;BIN:OUTSTD_LOGIC_VECTOR(5DOWNTO0);S:INSTD_LOGIC;CLR:INSTD_LOGIC;EC:INSTD_LOGIC;CY60:OUTSTD_LOGIC);ENDCOMPONE

7、NT;--子文件定义代码--***************************************************LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;--***************************************************ENTITYCOUNTER24ISPORT(CP:INSTD_LOGIC;BIN:O