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Verilog Coding Guidelines-Cisco

'Verilog Coding Guidelines-Cisco'
Document NumberENG-85857 RevisionB AuthorJane Smith A printed version of this document is an uncontrolled copy. Cisco Systems, Inc.Page 1 of 17 Verilog Coding Guidelines This document describes coding styles and guidelines for writing Verilog code for ASIC blocks and test benches. Reviewers ReviewerName and Title ASIC ManagerBob Parker, Mgr, Hardware Engineering Modification History RevDateOriginatorComments A10/30/00Jane SmithAdded test bench information on file name, reporting results B11/2/00Jane SmithAdded document number and sign-off page Document NumberENG-85857 RevisionB AuthorJane Smith A printed version of this document is an uncontrolled copy. Cisco Systems, Inc.Page 2 of 17 Table of Contents 1Overview.3 2Alignment/Space4 2.1Tabs 4 2.2Text file width. 4 2.3White space around operators 4 2.4Nested indentation levels. 4 2.5Alignment. 6 3Naming conventions8 3.1Modules/Variables 8 3.2Special Case Variables 8 3.2.1Clocks.8 3.2.2Flip-Flops i 10; i = i + 1 ) begin statement1; statement2; end statement3; statement4; end else statement5; Document NumberENG-85857 RevisionB AuthorJane Smith A printed version of this document is an uncontrolled copy. Cisco Systems, Inc.Page 5 of 17 Correct Example: if ( this ) begin for ( i == 0; i 10; i = i + 1 ) begin statement1; statement2; end statement3; statement4; end else begin statement5; end Case statements are a little more complex. The begin/end structure should always be used in a case definition, indentation levels should be used to offset the statements that are encapsulated, but the use of blank lines can be used or omitted to best show the statement groupings. Incorrect Example: case ( myBus[3:0] ) 4’b0000 :my_signal1 = TRUE; 4’b0001 :my_signal1 = FALSE; 4’b0010 : begin my_signal1 = TRUE; my_signal2 = FALSE; end 4’b0100 : my_signal2 = FALSE; default : my_signal1 = TRUE; endcase Document NumberENG-85857 RevisionB AuthorJane Smith A printed version of this document is an uncontrolled copy. Cisco Systems, Inc.Page 6 of 17 Correct Example: case ( myBus[3:0] ) 4’b0000 : begin my_signal1 = TRUE; end 4’b0001 : begin my_signal1 = FALSE; end 4’b0010 : begin my_signal1 = TRUE; my_signal2 = FALSE; end 4’b0100 : begin my_signal2 = FALSE; end default : begin my_signal1 = TRUE; end endcase 2.5 Alignment Aligning code statements can seem like a menial task, but it significantly adds to the under- standing of code. Alignment should be used in declarations, assignments, multi-line statements, and end of line comments. Incorrect Example: reg[3:0] my_signal1; reg[31:0] myDecodedSignal1; reg[4:0] my_signal2, my_signal3, my_signal4; wire[2:0] mySelect; Correct Example: //---------------------------------------------------------- // Signal Declarations: reg //---------------------------------------------------------- reg[3:0]my_signal1;//description reg[31:0]my_decoded_signal1; //description reg[4:0]my_signal2, //description regmy_signal3, //description regmy_signal4; //description //------------------------------------
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