EDA技术实用教程课后问题详解---潘松,黄继业.doc

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1、3-3给出一个4选1多路选择器的VHDL描述。选通控制端有四个输入：S0、S1、S2、S3。当且仅当S0=0时:Y=A；S1=0时:Y=B；S2=0时:Y=C；S3=0时:Y=D。--解：4选1多路选择器VHDL程序设计。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41aISPORT(A,B,C,D:INSTD_LOGIC;S0,S1,S2,S3:INSTD_LOGIC;Y:OUTSTD_LOGIC);ENDENTITYmux41a;ARCHITECTUREoneOFmux41aI

2、SSIGNALS0_3:STD_LOGIC_VECTOR(3DOWNTO0);BEGINS0_3<=S0&S1&S2&S3;y<=AWHENS0_3="0111"ELSEBWHENS0_3="1011"ELSECWHENS0_3="1101"ELSEDWHENS0_3="1110"ELSE'Z';ENDARCHITECTUREone;3-4给出1位全减器的VHDL描述；最终实现8位全减器。要求:1)首先设计1位半减器,然后用例化语句将它们连接起来,图4-20中h_suber是半减器,diff是输出差(diff=x-y),s_out是

3、借位输出(s_out=1,x

4、out<=(NOTx)ANDy;ENDARCHITECTUREhs1;--解(1.2)：采用例化实现图4-20的1位全减器LIBRARYIEEE;--1位二进制全减器顺层设计描述USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_suberISPORT(xin,yin,sub_in:INSTD_LOGIC;sub_out,diff_out:OUTSTD_LOGIC);ENDENTITYf_suber;ARCHITECTUREfs1OFf_suberISCOMPONENTh_suber--调用半减器声明语句PORT(

5、x,y:INSTD_LOGIC;diff,s_out:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALa,b,c:STD_LOGIC;--定义1个信号作为部的连接线。BEGINu1:h_suberPORTMAP(x=>xin,y=>yin,diff=>a,s_out=>b);u2:h_suberPORTMAP(x=>a,y=>sub_in,diff=>diff_out,s_out=>c);sub_out<=cORb;ENDARCHITECTUREfs1;(2)以1位全减器为基本硬件,构成串行借位的8位减法器,要求用

6、例化语句来完成此项设计(减法运算是x-y-sun_in=difft)。xinsub_outyinu0sub_indiff_outx0y0sindiff0xinsub_outyinu1sub_indiff_outx1y1diff1xinsub_outyinu7sub_indiff_outx7y7soutdiff7……………….……………….串行借位的8位减法器a0a1a6--解(2)：采用例化方法，以1位全减器为基本硬件；实现串行借位的8位减法器(上图所示)。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL

7、;ENTITYsuber_8ISPORT(x0,x1,x2,x3,x4,x5,x6,x7:INSTD_LOGIC;y0,y1,y2,y3,y4,y5,y6,y7,sin:INSTD_LOGIC;diff0,diff1,diff2,diff3:OUTSTD_LOGIC;diff4,diff5,diff6,diff7,sout:OUTSTD_LOGIC);ENDENTITYsuber_8;ARCHITECTUREs8OFsuber_8ISCOMPONENTf_suber--调用全减器声明语句PORT(xin,yin,sub_in:INS

8、TD_LOGIC;sub_out,diff_out:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALa0,a1,a2,a3,a4,a5,a6:STD_LOGIC;--定义1个信号作为部的连接线。BEGINu0:f_s