systemverilog快速入门ppt

《systemverilog快速入门ppt》由会员上传分享，免费在线阅读，更多相关内容在教育资源-天天文库。

1、SystemVerilog讲座第一讲:SystemVerilog基本知识夏宇闻神州龙芯集成电路设计公司2008VerilogHDL的发展历史1984:GatewayDesignAutomation推出Verilog初版1989:Gateway被CadenceDesignSystems公司收购1990:Cadence向业界公开VerilogHDL标准1993:OVI提升theVerilog标准，但没有被普遍接受1995:IEEE推出VerilogHDL(IEEE1364-1995)标准2001:IEEE推出VerilogIEEEStd1364-20

2、01标准2002:IEEE推出VerilogIEEEStd1364.1-2002标准2002:Accellera对SystemVerilog3.0进行标准化–Accellera是OVI&VHDLInternational(VI)合并后的国际标准化组织2003:Accellera标准化后的SystemVerilog3.12006:IEEE推出带SystemVerilog扩展的Verilog新标准为什么称SystemVerilog3.x?SystemVerilog是对Verilog革命性的扩展Verilog1.0-IEEE1364-1995“Veri

3、log-1995”标准–第一代IEEEVerilog标准Verilog2.0-IEEE1364-2001“Verilog-2001”标准–第二代IEEEVerilog标准–显著提升了Verilog-1995标准的性能SystemVerilog3.x-国际标准化组织对Verilog-2001的扩展–第三代Verilog标准–DAC-2002-SystemVerilog3.0–DAC-2003-SystemVerilog3.1SystemVerilog是Verilog-2001扩展后的超集assertionsmailboxestestprogramb

4、lockssemaphoresclockingdomainsconstrainedrandomvaluesprocesscontroldirectCfunctioncalls-----------------------SystemVerilog------------------------------------fromC/C++--------classesdynamicarraysinheritanceassociativearraysstringsreferencesSystemVerilog是Verilog-2001扩展后的超集int

5、erfacesdynamicprocessesnestedhierarchy2-statemodelingbyteunrestrictedportspackedarraysimplicitportconnectionsarrayassignmentsenhancedliteralsenhancedeventcontroltimevalues&unitsunique/prioritycase/iflogic-specificprocessesrootnamespacealiasconst&=

6、=^=%=-----------------------

7、---------------------------------------fromC/C++--------intglobalsbreakshortintenumcontinuelonginttypedefreturnBytestructuresdo-whileShortrealunions++--+=-=*=/=voidcasting>>=<<=>>>=<<<=aliasconst&=

8、=^=%=-------------------------SystemVerilog-------------------------------Syst

9、emVerilog是Verilog-2001扩展后的超集ANSICstyleportsstandardfileI/O(*attributes*)generate$value$plusargsconfigurationslocalparam`ifndef`elsif`linememorypartselectsconstantfunctions@*variablepartselect--------fromC/C++--------multidimensionalarrayssignedtypesAutomatic**(poweroperator)-

10、---------------------------------Verilog-2001-----------------------