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ID:32247838
大小:4.77 MB
页数:67页
时间:2019-02-02
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1、AThesisinComputerArchitectureWCETAnalysisofMulticoreReal—-TimeSystemswithSharedBusesByGuoYingSupervisor:ProfessorDengQingxuNortheasternUniversityJune2010WCETAnalysisofMulticoreReal—TimeSystemswithSharedBusesAbstractItispredictedthatmulticoreprocessorswillbeincreasinglyusedinfutureembedde
2、dreal—timesystemsforhighperformanceandlowenergyconsumption.T11emajorobstacleisthatpeoplemaynotpredictandprovideanypreciseguaranteeonreal—timepropertiesofthemulticorereal-timesystemsbecauseofthesharedresources.ThesharedmemorybusiSoneofthemostcriticalresourcesinthemulticoresystems.becausea
3、ll也ecorescarlaccesstheoff-chipmemoryonlywiththesharedbus.ButatthesalTletime,thesharedbusmayseverelydegradethetimingpredictabilityofthemulticorereal—timesystems.Tmsisbecausethatthebusdelayforeachcoremaynotbepreciselypredictedduetotheaccesscontentionbetweensomecores.Tosolvethisaboveproblem
4、,thisthesismainlyanalyzestheofthemulticorereal-timesystemwiththesharedbusesusingthemodelcheckingtechnique.T11isthesisstudiesamulticoresystemmodelwhereeachcorehasaprivatecacheandallcoresuseasharedbustoaccesstheoff-chipmemory.Fortheanalysisofthesystemmodel,thisthesisfirstlyu.sesabstractint
5、erpretationtechniquetoanalyzetheprivateinstructioncachebehaviorofaprogramrunningonadedicatedcore.Afterthat,wecanobtaintheinformationwhethereachinstructionoftheprogramisintheinstructionCacheornot.Basedonthesecacheanalysisresults.t11iSthesisthencarlconstructatimedautomatonforeachprogramrun
6、ninginthismulticoresystemwiththehelpofUPPAALmodelchecker.Theseautomatonsoftheprogramscanmodeltheprecisetiminginformationonwhentoaccessthememorybusforeachcore.ThethesisalsomodelsthebehaviorofthesharedbusinthemulticoresystemusingaUPPAAL’Stimedautomaton.Finally,thisthesisusesUPPAALtocheckth
7、ewholesystemmodelcomposedoftheautomatonsoftheprogramsandthesharedbus.Withthismethod,itcarlobtainthepreciseestimationofeachprogramrunninginthismulticoresystem新t11thesharedbus.Basedonthepresentedtechniques,thisthesishasdevelopedatoolforanalyzingtheofthemulticorereal—timesys
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