LVDS接收发送芯片DS90C

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1、Link-85MHz,+3.3VProgrammableLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-85MHzDS90C385/DS90C365+3.3VProgrammableLVDSTransmitter24-BitFlatPanelDisplay(FPD)May2003DS90C385/DS90C365+3.3VProgrammableLVDSTransmitter24-BitFlatPanelDisplay(FPD)Link-85MHz,+3.3VProgrammab

2、leLVDSTransmitter18-BitFlatPanelDisplay(FPD)Link-85MHzGeneralDescriptionThischipsetisanidealmeanstosolveEMIandcablesizeproblemsassociatedwithwide,high-speedTTLinterfaces.TheDS90C385transmitterconverts28bitsofLVCMOS/LVTTLdataintofourLVDS(LowVoltageDifferentialSignal

3、-Featuresing)datastreams.Aphase-lockedtransmitclockistransmit-tedinparallelwiththedatastreamsoverafifthLVDSlink.n20to85MHzshiftclocksupportEverycycleofthetransmitclock28bitsofinputdataarenBestinClassSet&HoldTimesonTxINPUTssampledandtransmitted.Atatransmitclockfrequ

4、encyof85nTxpowerconsumption<130mW(typ)@85MHzMHz,24bitsofRGBdataand3bitsofLCDtimingandGrayscalecontroldata(FPLINE,FPFRAME,DRDY)aretransmittedatnTxPower-downmode<200µW(max)arateof595MbpsperLVDSdatachannel.Usinga85MHznSupportsVGA,SVGA,XGAandDualPixelSXGA.clock,thedata

5、throughputis297.5Mbytes/sec.Alsoavail-nNarrowbusreducescablesizeandcostableistheDS90C365thatconverts21bitsofLVCMOS/nUpto2.38GbpsthroughputLVTTLdataintothreeLVDS(LowVoltageDifferentialSig-nUpto297.5Megabytes/secbandwidthnaling)datastreams.Bothtransmitterscanbeprogra

6、mmedforRisingedgestrobeorFallingedgestrobethroughan345mV(typ)swingLVDSdevicesforlowEMIdedicatedpin.ARisingedgeorFallingedgestrobetransmit-nPLLrequiresnoexternalcomponentsterwillinteroperatewithaFallingedgestrobeReceivernCompatiblewithTIA/EIA-644LVDSstandard(DS90CF3

7、86/DS90CF366)withoutanytranslationlogic.nLowprofile56-leador48-leadTSSOPpackageTheDS90C385isalsoofferedina64ball,0.8mmfinepitchnDS90C385alsoavailableina64ball,0.8mmfinepitchballgridarray(FBGA)packagewhichprovidesa44%ballgridarray(FBGA)packagereductioninPCBfootprint

8、comparedtotheTSSOPpackage.BlockDiagramsDS90C385DS90C3651008680110086829OrderNumberDS90C385MTDorDS90C385SLCOrderNumberDS90C365MTDSeeNSPackageNumbe