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1、SEQCPUImplementationWhatwewilldiscusstoday?TheimplementationofasequentialCPU----SEQEveryInstructionfinishedinonecycle.InstructionexecutesinsequentialNotwoinstructionexecuteinparalleloroverlapAnrevisedversionofSEQ----SEQ+ModifythePCUpdatestageofSEQtoshowthedifferencebetweenISAandimplementationSome
2、MacrosNameValueMeaningINOP0CodefornopinstructionIHALT1CodeforhaltinstructionIRRMOVL2CodeforrrmovlinstructionIIRMOVL3CodeforirmovlinstructionIRMMOVL4CodeforrmmovlinstructionIMRMOVL5CodeformrmovlinstructionIOPL6CodeforintegeropinstructionsIJXX7Codeforjumpinstructions……………………………………………IPOPLBCodeforpo
3、plinstructionRESPRENONE68RegisterIDfor%espIndicatesnoregisterfileaccessALUADD0FunctionforadditionoperationInstructionmemoryInstructionmemoryPCincrementPCincrementCCCCALUALUDatamemoryDatamemoryFetchDecodeExecuteMemoryWritebackicode,ifunrA,rBvalCRegisterfileRegisterfileABMERegisterfileRegisterfileA
4、BMEPCvalPsrcA,srcBdstA,dstBvalA,valBaluA,aluBBchvalEAddr,DatavalMPCvalE,newPCvalMSEQHardwareStructureStagesFetchReadinstructionfrommemoryDecodeReadprogramregistersExecuteComputevalueoraddressMemoryReadorwritedataWriteBackWriteprogramregistersPCUpdateprogramcounterInstructionFlowReadinstructionata
5、ddressspecifiedbyPCProcessthroughstagesUpdateprogramcounterInstructionmemoryInstructionmemoryPCincrementPCincrementCCCCALUALUDatamemoryDatamemoryFetchDecodeExecuteMemoryWritebackicode,ifunrA,rBvalCRegisterfileRegisterfileABMERegisterfileRegisterfileABMEPCvalPsrcA,srcBdstA,dstBvalA,valBaluA,aluBBc
6、hvalEAddr,DatavalMPCvalE,valMnewPCDifferencebetweensemanticsandimplementationISAEverystagemayupdatesomestates,theseupdatesoccursequentiallySEQAllthestateupdateoperationsoccursimultaneouslyatclockrising(exceptCC)SEQHardwareKeyBlueboxes:predesignedhardwareblocksE.g.,memories,ALUGrayboxes:controllog
7、icDescribeinHCLWhiteovals:labelsforsignalsThicklines:32-bitwordvaluesThinlines:4-8bitvaluesDottedlines:1-bitvaluesFetchLogicPredefinedBlocksPC:RegistercontainingPCInstructionmemory:Read6bytes(PCtoPC+5)Split:Divideinstr
