外文翻译-中英文对照AVR单片机

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1、AVRCPUCoreIntroductionThissectiondiscussestheAVRcorearchitectureingeneral.ThemainfunctionoftheCPUcoreistoensurecorrectprogramexecution.TheCPUmustthereforebeabletoaccessmemories,performcalculations,controlperipherals,andhandleinterrupts.ArchitecturalOverviewFigure3.BlockDiagramoftheAVRMCUArch

2、itectureInordertomaximizeperformanceandparallelism,theAVRusesaHarvardarchitecture–withseparatememoriesandbusesforprogramanddata.Instructionsintheprogrammemoryareexecutedwithasinglelevelpipelining.Whileoneinstructionisbeingexecuted,thenextinstructionispre-fetchedfromtheprogrammemory.Thisconce

3、ptenablesinstructionstobeexecutedineveryclockcycle.TheprogrammemoryisIn-SystemReprogrammableFlashmemory.Thefast-accessRegisterFilecontains32x8-bitgeneralpurposeworkingregisterswithasingleclockcycleaccesstime.Thisallowssingle-cycleArithmeticLogicUnit(ALU)operation.InatypicalALUoperation,twoop

4、erandsareoutputfromtheRegisterFile,theoperationisexecuted,andtheresultisstoredbackintheRegisterFile–inoneclockcycle.Sixofthe32registerscanbeusedasthree16-bitindirectaddressregisterpointersforDataSpaceaddressing–enablingefficientaddresscalculations.Oneofthetheseaddresspointerscanalsobeusedasa

5、naddresspointerforlookuptablesinFlashProgrammemory.Theseaddedfunctionregistersarethe16-bitX-,Y-,andZ-register,describedlaterinthissection.TheALUsupportsarithmeticandlogicoperationsbetweenregistersorbetweenaconstantandaregister.SingleregisteroperationscanalsobeexecutedintheALU.AfterFlashProgr

6、amMemoryInstructionRegisterInstructionDecoderProgramCounterControlLines32x8GeneralPurposeRegistrersALUStatusandControlI/OLinesEEPROMDataBus8-bitDataSRAMDirectAddressingIndirectAddressingInterruptUnitSPIUnitWatchdogTimerAnalogComparatorI/OModule2I/OModule1I/OModulen9ATmega16(L)2466N–AVR–10/06

7、anarithmeticoperation,theStatusRegisterisupdatedtoreflectinformationabouttheresultoftheoperation.Programflowisprovidedbyconditionalandunconditionaljumpandcallinstructions,abletodirectlyaddressthewholeaddressspace.MostAVRinstructionshaveasingle16-bi