Digital Design and FPGA数值设计与FPGA

Digital Design and FPGA数值设计与FPGA

ID:39065582

大小:366.40 KB

页数:22页

时间:2019-06-24

Digital Design and FPGA数值设计与FPGA_第1页
Digital Design and FPGA数值设计与FPGA_第2页
Digital Design and FPGA数值设计与FPGA_第3页
Digital Design and FPGA数值设计与FPGA_第4页
Digital Design and FPGA数值设计与FPGA_第5页
资源描述:

《Digital Design and FPGA数值设计与FPGA》由会员上传分享,免费在线阅读,更多相关内容在学术论文-天天文库

1、DigitalDesignandFPGAImplementationofaWirelessVideoSurveillanceSystemVivekShahNoelCampbellRaymondTongIntroductoryDigitalSystemsLaboratory5/19/2006Abstract:ThislaboratoryusedaXilinxFPGAtocreateavideosurveillancesystemwithwirelesstransmissionasadigitalc

2、ircuit.Thesurveillancesystemwasfullyfunctionalandabletocapture,encode,andtransmitandimage,aswellasreceive,decode,anddisplaytheimage.ModelSimsimulationswereusedtotestthevariousmodulesofthesurveillancesystem,aswellasVerilogtestbenches.Afteracomprehensi

3、vesuiteoftestsfoundnoerrorsinthedesign,thesurveillancesystemwasprogrammedintoaFPGAandpassedphysicaltestingaswell.TableofContents1.TitlePageandAbstract12.TableofContents23.ListofFigures,Tables,andEquations34.OperationalOverview45.ModuleDescriptionandI

4、mplemention5a.Capture-Encode-TransmitSystem5i.VideoCapture51.NTSCDecoder52.Store6463.SetAddress64.VGAController75.Delay76.YCrCbtoRGBconverter77.Display7ii.VideoMemory(Encoder)8iii.Encoder81.DCTMultiply10a.DCTFront10b.DCTTable10c.MultiplierShiftRegist

5、er10d.DCTBack102.Encode_memory_register113.Encode_FSM11iv.WirelessBlockMemory12v.WirelessTransmitter121.TransmitterControlUnit13a.TXShiftRegister13b.RS232Sender13vi.WirelessPacketSender14b.Receiver-Decode-DisplaySystem14i.WirelessReceiver141.PacketRe

6、ceiver142.ReceiverControlUnit14a.RS232Receiver14b.RXShiftRegister14ii.WirelessBlockMemory(Decoder)15iii.Decoder151.DCTMultiplyDecode16a.DCTFrontDecode16b.DCTTable16c.MultiplierShiftRegister16d.DCTBackDecode162.DecoderFSM17iv.VideoMemory(Decode)17v.Vi

7、deoDisplay171.Read64186.TestingandDebugging197.Conclusion228.Appendix232ListofFiguresFigure1–SystemDiagram................................................................................................................................................

8、.........4Figure2–BlockdiagramofVideoCaptureModule..................................................................................................................5Figure3–SetAddressFiniteStateMachine.................................................

当前文档最多预览五页,下载文档查看全文

此文档下载收益归作者所有

当前文档最多预览五页,下载文档查看全文
温馨提示:
1. 部分包含数学公式或PPT动画的文件,查看预览时可能会显示错乱或异常,文件下载后无此问题,请放心下载。
2. 本文档由用户上传,版权归属用户,天天文库负责整理代发布。如果您对本文档版权有争议请及时联系客服。
3. 下载前请仔细阅读文档内容,确认文档内容符合您的需求后进行下载,若出现内容与标题不符可向本站投诉处理。
4. 下载文档时可能由于网络波动等原因无法下载或下载错误,付费完成后未能成功下载的用户请联系客服处理。