《EDA课后作业》PPT课件

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1、4-1画出与下例实体描述对应的原理图符号元件：ENTITYbuf3sIS--实体1：三态缓冲器PORT(input:INSTD_LOGIC;--输入端enable:INSTD_LOGIC;--使能端output:OUTSTD_LOGIC);--输出端ENDbuf3x;ENTITYmux21IS--实体2：2选1多路选择器PORT(in0,in1,sel:INSTD_LOGIC;output:OUTSTD_LOGIC);4-2.图4-17所示的是4选1多路选择器，试分别用IF_THEN语句和CASE语句的表达方式写出此电路的VHDL程序。选择控制的信号s

2、1和s0的数据类型为STD_LOGIC_VECTOR；当s1='0'，s0='0'；s1='0'，s0='1'；s1='1'，s0='0'和s1='1'，s0='1'分别执行y<=a、y<=b、y<=c、y<=d。图4-174选1多路选择器使用IF…THEN语句：Libraryieee;useieee.std_logic_1164.alll;Entitymux41isPort(s0,s1,a,b,c,d:instd_logic;y:outstd_logic);Endmux41;Architectureoneofmux41isSignals10:std_

3、logic_vector(1downto0);Begins10<=s1&s0;process(s10,a,b,c,d)beginifs10=“00”theny<=a;elsifs10=“01theny<=b;elsifs10=“10”theny<=c;elsey<=d;endif;endprocess;Endone;使用CASE语句：Libraryieee;useieee.std_logic_1164.alll;Entitymux41isPort(s0,s1,a,b,c,d:instd_logic;y:outstd_logic);Endmux41;Ar

4、chitectureoneofmux41isSignals10:std_logic_vector(1downto0);Begins10<=s1&s0;process(s10,a,b,c,d)begincases10iswhen“00”=>y<=a;when“01”=>y<=b;when“10”=>y<=c;whenothers=>y<=a;endcase;endprocess;Endone;KX康芯科技4-3.图4-18所示的是双2选1多路选择器构成的电路MUXK，对于其中MUX21A，当s='0'和'1'时，分别有y<='a'和y<='b'。试在一个

5、结构体中用两个进程来表达此电路，每个进程中用CASE语句描述一个2选1多路选择器MUX21A。图4-18双2选1多路选择器Libraryieee;useieee.std_logic_1164.alll;EntitymuxkisPort(s0,s1,a1,a2,a3:instd_logic;outy:outstd_logic);Endmuxk;ArchitectureoneofmuxkisSignaltmp:std_logic;Beginprocess(s0,a2,a3)begincases0iswhen‘0’=>tmp<=a2;when‘1’=>tmp

6、<=a3;endcase;endprocess;process(s1,a1,tmp)begincases1iswhen‘0’=>outy<=a1;when‘1’=>outy<=tmp;endcase;endprocess;Endone;Libraryieee;useieee.std_logic_1164.alll;Entitymux21isport(s,a,b:instd_logic;y:outstd_logic);Endmux21;Architectureoneofmux21isBeginy<=awhens=‘0’elseb;Endone;Libra

7、ryieee;useieee.std_logic_1164.alll;EntitymuxkisPort(s0,s1,a1,a2,a3:instd_logic;outy:outstd_logic);Endmuxk;ArchitecturebehofmuxkisComponentmux21port(s,a,b:instd_logic;y:outstd_logic);Endcomponent;Signaltmp:std_logic;BeginU1:mux21portmap(a=>a2,b=>a3,s=>s0,y=>tmp);U2:mux21portmap(a

8、=>a1,b=>tmp,s=>s1,y=>outy);Endbeh;4-4.图4-19是一个含