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1、∗低功耗高速缓存无效缓存路访问混合过滤机制研究1,2+1,5314范灵俊,徐远超,施巍松，范东睿,娄杰1(中国科学院计算技术研究所计算机体系结构国家重点实验室,北京100190)2(中国科学院研究生院,北京100049)3(韦恩州立大学计算机科学技术系,美国)4(英特尔公司,北京,100190)5(首都师范大学,信息工程学院,北京,100048)LowPowerCacheArchitectureswithHybridApproachofFilteringUnnecessary*WayAccesses1,2+1,5314FANLing-Jun,XUYuan
2、-Chao,SHIWei-Song,FANDong-Rui,LOUJie1(StateKeyLaboratoryofComputerArchitecture,ICT,CAS,Beijing100190,China)2(GraduateUniversityofChineseAcademyofSciences,Beijing,100049,China)3(DepartmentofComputerScience,WayneStateUniversity,DetroitMI-48202,USA)4(IntelCorporation,Beijing,100190,
3、China)5(CollegeofInformationEngineering,CapitalNormalUniversity,Beijing100048,China)+Correspondingauthor:Phn:+86-10-62600611,Fax:+86-10-62600600,E-mail:fanlingjun@ict.ac.cnReceived2012-07-04;Accepted2012-09-16Abstract:Powerhasbeenabigissueinprocessordesignforseveralyears.Ascaches
4、accountformoreandmoreCPUdieareaandpower,thispaperpresentsusingfilteringunnecessarywayaccessestoreducedynamicpowerconsumptionofcachessharedbyinstructionanddata.OurmethodsincludeusingInvalidFilter,whichcouldeliminateaccessestocachewayscontainedinvalidblocks,andI/DFilter,whichcoulde
5、liminateaccessestocachewayscontainedinstruction/dataaccesstypemismatchblocks,andTag-2Filter,whichcouldeliminateaccessestocachewayscontainedtaglowest2bitsmismatchblocks.Sincethemethodsreducingtheactivitieshappenedincachearchitecture,dynamicalCPUpowercouldbesignificantlydecreased.I
6、nthepaper,wealsoproposecombingtheabovemethodstogether,whichiscalledInvalid+I/D+Tag-2Filter,inanattempttoachievebetterpowersavingresults.Ourevaluationsshowthat,wecouldobtain19.6%-47.8%(whichisonaverage34.3%)improvementona64K-4wayset-associativecacheand19.6%-55.2%(whichisonaverage3
7、9.2%)improvementona128k-8wayset-associativecachecomparingtoInvalid+I/DFilter,and6.1%-27.7%(whichisonaverage16.6%)improvementona64K-4wayset-associativecacheand6.9%-44.4%(whichisonaverage25.0%)improvementona128k-8wayset-associativecachecomparingtoInvalid+Tag-2Filter,respectively.∗本
8、文得到国家“973”重点基础研究发展规划项目基金(2011CB302501),国
