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1、------------------------------------------作者xxxx------------------------------------------日期xxxxverilog数字钟代码【精品文档】moduledigclk(clk,en,rst,dula,wela,s1,s2,s3,led,flag1,start1,flag2,start2,aled,s6,s4,s5);//s1调时s2调分s3调秒wela位码dula段码en使能clk时钟,flag1是跑表标志（拨上去就是显示跑表），置一为跑表功能,
2、start1为跑表开始停止//flag2为闹钟标志（拨上去就是设置闹钟时间）start2为闹钟开关aled闹钟提示灯inputclk,rst,en,s1,s2,s3,flag1,start1,flag2,start2,s6,s4,s5;output[2:0]wela;output[7:0]dula;outputled;outputaled;regled;regaled;reg[7:0]cnt,dula;reg[2:0]wela;reg[7:0]hourh,hourl,minh,minl,sech,secl;reg[7:0]phou
3、rh,phourl,pminh,pminl,psech,psecl;reg[7:0]ahourh,ahourl,aminh,aminl,asech,asecl;reg[3:0]a;//a用于数码管显示的临时变量(*synthesis,keep*)regclk1;always@(posedgeclk1)beginif(start2)beginif(hourh==ahourh&&hourl==ahourl&&minh==aminh&&minl==aminl&&sech==asech&&secl==asecl)aled=1'b1;els
4、ealed=1'b0;endendalways@(posedgeclk1)//闹钟功能beginif(flag2)beginif(!s4)//调节小时【精品文档】【精品文档】begin/*if(ahourl==9)beginahourl<=0;ahourh<=ahourh+1;endif(ahourh==2&&ahourl==3)beginahourh<=0;ahourl<=0;endelseahourl<=ahourl+1;*/ahourl<=ahourl+1;if(ahourl==3&&ahourh==2)beginahour
5、l<=0;ahourh<=0;endif(ahourl==9)beginahourl<=0;ahourh<=ahourh+1;end;endelseif(!s5)//调节分钟beginif(aminl==9)beginaminl<=0;if(aminh==5)aminh<=0;elseaminh<=aminh+1;endelseaminl<=aminl+1;endelseif(!s6)//调节秒钟（调节都是在暂停的前提下）beginif(asecl==9)beginasecl<=0;if(asech==5)asech<=0;els
6、easech<=asech+1;endelseasecl<=asecl+1;endendendalways@(posedgeclk1)//用于跑表beginif(flag1&&start1)begin【精品文档】【精品文档】if(psecl==9)//时钟正常跳动状态beginpsecl<=0;if(psech==5)beginpsech<=0;if(pminl==9)beginpminl<=0;if(pminh==5)beginpminh<=0;if(phourl==9)beginphourl<=0;phourh<=phourh
7、+1;endelseif(phourh==2&&phourl==3)beginphourl<=0;phourh<=0;endelsephourl<=phourl+1;endelsepminh<=pminh+1;endelsepminl<=pminl+1;endelsepsech<=psech+1;endelsepsecl<=psecl+1;endelseif(!flag1)beginpsecl<=0;psech<=0;pminl<=0;pminh<=0;phourl<=0;phourh<=0;endendalways@(posed
8、geclk)//用于分频begincnt=cnt+1;if(cnt==200)beginclk1=1'b1;cnt=0;endelseclk1=1'b0;//200分频，CLK为数码管扫描频率，CLK1为计数频率if(wela<7)wela=wel
