fpga接口解决方案

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1、NationalSemiconductor’sInterfaceSolutionsforXilinxFPGAsMarch20071Agenda•InterfaceOverview•ExternalSerDes•SignalconditioningapplicationswithFPGAs•ExtendingPCI-ExpressinSpartanIII•RocketI/Osolutions•SolutionsforSDIapplications•ClockConditioners•Ethernet10/100PHY•Conclusions2NationalSemiconductorCorp

2、orationConfidentialNationalSemiconductorInterfaceProductOverview3NationalSemiconductorCorporationConfidentialTrendTowardsSerialI/OasDataThroughputIncreases●TraditionalBuses●SerialI/OBuses–ParallelDataChannelstimedwitha–Embedtheclockinthedataparallelclock–ThroughputscaleseasilyCLK●Problemsaddingthr

3、oughput●Advantages–Increasingdatarateperpin–Eliminatesskewandsimultaneous¾simultaneousswitchingnoiseswitchingnoise–Increasebuswidth–Greaterdistance¾Addspincount-unreliable–GroupMultiplelinksforgreaterthroughput¾Packagesize/costincrease¾Skewbetweendataandclock4NationalSemiconductorCorporationConfid

4、entialDataTransmissionIssuesRequiringInterfaceSolutions1.ReducenoisefromSimultaneouslySwitchingOutputs(SSO)–Avoiddrivingtransmissionlineswithhighcurrentoutputs2.LVDS-Serializingdatato/fromlower-costFPGA–Usestand-aloneSerDesandPHYstotransferdataefficiently3.Increasedataratesignalingandreliabilityon

5、mid-rangeFPGA–UseCMLSignalconditionersandSerDes4.Protectfromoff-boardESDeventsinruggedapplications5.LowerpincounttoreduceFPGAandCPLDcost–Distributemultiplecopiesofdataandclock5NationalSemiconductorCorporationConfidentialSystemlevelissuesEnableSerDesperformancewithalowercostFPGAandreduceSSOnoiseAdv

6、antagesUselowercostFPGAReducedCurrentReduceoutputcurrentonFPGALVCMOSSERIALLVDSReliablehighperformanceDeserializerBACKPLANEInterfaceHighESDtoleranceatboardedgeSpartanLVDSEmbeddedClock,CommonSerDesDevicesFPGAorChannelLinkEMBEDDEDCLOCKSerDes10-bitSerandDes–SCAN921025/12261:10Deserialer,6Ch–SCAN926260

7、LVDSSpartanEmbeddedClock,10:1Serializer,8Ch–SCAN928028FPGAorChannelLink16-BitSerDes–DS92LV16SerDes18-BitSerDes–DS92LV1818-BitSerializer,2Ch–SCAN92182124-BitSerandDes_DS90C124/241CHANNELLINK21:3SerandDes–DS90CR21x