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1、ProbabilisticSimulationforReliabilityAnalysisofCMOSVLSICircuitsbyyzzyFaridN.Najm,RichardBurch,PingYang,andIbrahimN.HajjyzCoordinatedScienceLaboratoryVLSIDesignLaboratoryUniversityofIllinoisatUrbana-ChampaignTexasInstrumentsInc.Urbana,Illinois61801Dallas,Texas75265AbstractAnovelcurrent-estimation
2、approachisdevelopedtosupporttheanalysisofelectromi-grationfailuresinpowersupplyandgroundbussesofCMOSVLSIcircuits.Itusestheoriginalconceptofprobabilisticsimulationtoecientlygenerateaccurateestimatesoftheexpectedcurrentwaveformrequiredforelectromigrationanalysis.Assuch,theapproachispattern-indepe
3、ndentandrelievesthedesignerofthetedioustaskofspecifyinglogicalinputwaveforms.ThisapproachhasbeenimplementedintheprogramCRESTwhichhasshownexcellentaccuracyanddramaticspeedupscomparedtotraditionalapproaches.Wedescribetheapproachanditsimplementation,andpresenttheresultsofnumerousCRESTrunsonrealcirc
4、uits.F.NajmisnowwiththeVLSIDesignLaboratory,TexasInstrumentsInc.,Dallas,Texas75265ThisworkwassupportedbyTexasInstrumentsIncorporated,andtheUSAirForceRomeAirDevelopmentCenter.1IntroductionThereliabilityofintegratedcircuitsisamajorconcernfortheelectronicsindustry.Ashigherlevelsofintegrationareused
5、,theminimumlinewidthandlineseparationwilldecrease,therebyincreasingthechipfailurerate.Thisindicatesthattheimportanceofreliabilitycanonlyincreaseinthefuture.Itis,therefore,imperativethatcircuitsaredesignedwithreliabilityinmind.Thisworkaddresseselectromigration[1,2](EM),whichisamajorreliabilitypro
6、blemcausedbythetransportofatomsinametallineduetotheelectron
ow.Underpersistentcurrentstress,thiscancausedeformationsofthemetalleadingtoeithershortoropencircuits.ThefailurerateduetoEMdependsonthecurrentdensityinthemetallinesandisusuallyexpressedasamediantime-to-failure(MTF).Thereisade niteneedfor
7、CADtoolsthatpredictthesusceptibilityofagivendesigntoEMfailures.Asimulationtool,SPIDER[3],hasbeendevelopedtoestimatetheMTFforeachsectionofametalbuscorrespondingtoanyuser-selectedinterconnectsignal.Itrequirestheusertospecifycu
