eda教案(图和例题)

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1、附录程序源码及实验设计参考：1．基本门电路实验libraryieee;useieee.std_logic_1164.all;entitygateisport(signala:instd_logic;signalb:instd_logic;signaly:outstd_logic_vector(3downto0));endgate;architecturegateofgateisbeginprocess(a,b)beginy(3)<=nota;y(2)<=aandb;y(1)<=aorb;y(0)<=axorb;endprocess;e

2、ndgate;2．3/8译码器实验libraryieee;useieee.std_logic_1164.all;entitydecoderisport(signalsel:instd_logic_vector(2downto0);signalen:instd_logic;signaly:outstd_logic_vector(7downto0));enddecoder;architecturebehaviorofdecoderisbeginprocess(sel,en)beginy<="11111111";if(en='1')then

3、caseseliswhen"000"=>y(0)<='0';--0bitofoutputis0when"001"=>y(1)<='0';when"010"=>y(2)<='0';when"011"=>y(3)<='0';when"100"=>y(4)<='0';when"101"=>y(5)<='0';when"110"=>y(6)<='0';when"111"=>y(7)<='0';--7bitofoutputis0whenothers=>null;endcase;endif;endprocess;endbehavior;3．BCD

4、/七段显示译码器实验libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;entitybcdisport(d:instd_logic_vector(3downto0);en:instd_logic;data_out:outstd_logic_vector(7downto0));endbcd;architecturebcdofbcdisbeginprocess(d,en)beginif(en='1')then--signalenablecasediswhen

5、"0000"=>data_out<="00111111";--signaloutput:0when"0001"=>data_out<="00000110";when"0010"=>data_out<="01011011";when"0011"=>data_out<="01001111";when"0100"=>data_out<="01100110";when"0101"=>data_out<="01101101";when"0110"=>data_out<="01111101";when"0111"=>data_out<="0000

6、0111";when"1000"=>data_out<="01111111";when"1001"=>data_out<="01100111";--signaloutput:9whenothers=>data_out<="11111111";endcase;endif;endprocess;endbcd;4．计数器实验libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycounterisport(signalreset:instd_lo

7、gic;signalen:instd_logic;signalclk:instd_logic;signalclk_out:outstd_logic);endcounter;architecturebehaviorofcounterissignalcount:integerrange0to9;beginprocess(clk,en)beginifclk'eventandclk='1'thenifreset='1'thenclk_out<='0';count<=0;elsifen='1'thenifcount<9thencount<=co

8、unt+1;clk_out<='0';elsecount<=0;clk_out<='1';endif;endif;endif;endprocess;endbehavior;5．模拟74ls160计数器实验libraryi