eda实验程序及仿真波形图

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1、本课程设计的VHDL程序，仿真波形及实验输出波形libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityMGPPisport(input:instd_logic_vector(4downto0);clk,f1:instd_logic;f2:instd_logic_vector(1downto0);fout:outintegerrange255downto0);END;architectureoneofMGPPissignalq1,q2:integ

2、errange255downto0;signalD,d2:integerrange255downto0;signalfull:std_logic;signals1,s2,s3,s4:integerrange255downto0;beginprocess(clk)variabler1:std_logic_vector(4downto0);beginifclk'eventandclk='1'thenifr1="11111"thenr1:=input;full<=notfull;elser1:=r1+1;full<='0';endif;endif

3、;ENDPROCESS;PROCESS(full)variabler2:integerrange255downto0;beginiffull'eventandfull='1'thenifr2<255thenr2:=r2+1;elser2:=0;endif;endif;iff1='1'thenq1<=r2;elseq2<=r2;endif;endprocess;PROCESS(q1)BEGINCASEq1ISWHEN00=>D<=127;WHEN01=>D<=130;WHEN02=>D<=133;…….WHEN255=>D<=117;WHEN

4、OTHERS=>NULL;ENDCASE;ENDPROCESS;process(f2)begincasef2iswhen"00"=>s1<=255;s2<=0;s3<=0;s4<=0;when"01"=>s1<=255;s2<=255;s3<=0;s4<=0;when"10"=>s1<=255;s2<=255;s3<=255;s4<=0;when"11"=>s1<=255;s2<=255;s3<=255;s4<=255;whenothers=>null;endcase;endprocess;process(q2)BEGINcaseq2isW

5、HEN00=>D2<=s1;WHEN01=>D2<=s1;WHEN02=>D2<=s1;….WHEN48=>D2<=s1;WHEN49=>D2<=s1;WHEN50=>D2<=s1;WHEN51=>D2<=s2;WHEN52=>D2<=s2;WHEN53=>D2<=s2;WHEN54=>D2<=s2;…..…..WHEN66=>D2<=s2;WHEN67=>D2<=s2;WHEN68=>D2<=s2;WHEN69=>D2<=s2;WHEN102=>D2<=s2;WHEN103=>D2<=s2;WHEN104=>D2<=s2;WHEN105=

6、>D2<=s3;WHEN106=>D2<=s3;WHEN107=>D2<=s3;WHEN108=>D2<=s3;…..…...WHEN151=>D2<=s3;WHEN152=>D2<=s3;WHEN153=>D2<=s3;WHEN154=>D2<=s3;WHEN155=>D2<=s4;WHEN156=>D2<=s4;WHEN157=>D2<=s4;WHEN158=>D2<=s4;WHEN159=>D2<=s4;…..……WHEN217=>D2<=s4;WHEN218=>D2<=s4;WHEN219=>D2<=s4;WHEN220=>D2<=

7、s4;WHEN221=>D2<=0;WHEN222=>D2<=0;WHEN223=>D2<=0;………….WHEN253=>D2<=0;WHEN254=>D2<=0;WHEN255=>D2<=0;WHENOTHERS=>NULL;ENDCASE;endprocess;PROCESS(D,D2)BEGINIFf1='1'THENfout<=D;ELSEfout<=D2;ENDIF;ENDPROCESS;END;图1.17分频时正弦波形输出图2.32分频和20分频正弦输出图3.仿真波形正弦波各分频概况图4.正弦波2分频的波形输出图5.方波不同占

8、空比波形图6.频率为2.8KHZ的正弦波形输出图7.频率为4.7KHZ的正弦输出波形图8.占空比为1/5的方波输出波形图9.占空比为2/5方波输出波形