基于vhdl的数字钟的设计说明书

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1、课程设计报告设计题目：用VHDL语言实现数字钟的设计班级：电子1101学号：20113078姓名：李玉珍指导教师：李世平、李宁设计时间：2014年1月16摘要随着IT行业的不断发展EDA技术在很多行业得到了广泛的应用，在很多大学也开设了相应的课程，但只有理论知识不足以应对实际项目的开发，不足以胜任更加庞大的系统开发。本次课程设计旨在提高学生的实际动手能力和解决问题的能力。本次课程设计主要使用实验室提供的XiLinx公司的ISE14.2作为编写程序和仿真的平台来实现数字钟的设计。该项目的实际设计中，就整体框架的设计，软件的开发，仿真

2、等过程进行了一一验证。在数字钟的设计中应用了元件例化的整体思路实现，实现过程可分为分频模块，时分秒计数模块，时分秒置数模块，年月日计数模块，年月日置数模块，整点报时模块，时间显示切换模块等。用6个数码管显示时分秒，set按钮产生第一个脉冲时，显示切换年月日，第2个脉冲到来时可预置年份，第3个脉冲到来时可预置月份，依次第4、5、6、7个脉冲到来时分别可预置日期、时、分、秒，第8个脉冲到来后预置结束，正常工作，显示的是时分秒。tn为高电平时，upd0有脉冲到达时，预置位加1.否则减1.关键词：数字钟，ISE平台，元件例化目录16摘要·

3、·····························································21、课程设计目的···················································42、课程设计内容及要求············································42.1设计任务要求················································42.2提高的内容及要求·····················

4、·······················43、VHDL程序设计···················································53.1设计方案····················································53.1.1分频模块··············································53.1.2时分秒计数模块········································63.1.3时分秒置数模块·

5、······································73.1.4年月日计数模块········································83.1.516年月日置数模块········································93.1.6选择器模块···········································103.1.7时间显示模块·········································123.1.8整点报时模块·

6、········································133.1.9元件例化模块·········································144、仿真与分析······················································164.1分频模块仿真波形···········································164.2时分秒计数模块仿真波形·····································17

7、4.3时分秒置数模块仿真波形·····································174.4年月日计数模块仿真波形·····································184.5年月日置数模块仿真波形·····································184.6整点报时模块的仿真波形·····································195、设计结果16················································

8、········196、课程设计总结，包括.收获、体会和建议·····························197、参考文献························································2