可重构硬件容错技术-研究

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1、可重构硬件容错技术研究图3.23故障线网取消与重布线过程的ModelSim仿真结果..................................................29图4.1可编程单元结构...............................................................................................................32图4.2可配置逻辑子模块结构................................................

2、...................................................33图4.3可配置逻辑块结构...........................................................................................................33图4.4布线开关模块结构.............................................................................................

3、..............34图4.5自修复控制单元结构框图...............................................................................................34图4.6配置层结构.......................................................................................................................35图4.7布线信息寄存器组的组织结构....

4、...................................................................................35图4.8布线信息寄存器...............................................................................................................36图4.9布线层电路结构简化图........................................................

5、...........................................36图4.10双模冗余结构.................................................................................................................38图4.114×4并行乘法器结构.............................................................................................

6、.........40图4.124位并行乘法器在自重构单元阵列的布局布线图......................................................40图4.134位并行乘法器布局布线后功能仿真图......................................................................41图4.144位并行乘法器故障自修复过程仿真图......................................................................

7、41图4.15容错后4位并行乘法器功能仿真图.............................................................................42图4.16容错后4位并行乘法器在自重构单元阵列的布局布线图.........................................42图4.174位串-并行乘法器结构..........................................................................................

8、......43图4.184位串-并行乘法器在自重构单元阵列的布局布线图...........