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1、IEICETRANS.FUNDAMENTALS,VOL.E82–A,NO.11NOVEMBER19992366PAPERSpecialSectiononVLSIDesignandCADAlgorithmsAMemoryPowerOptimizationTechniqueforApplicationSpecificEmbeddedSystemsTohruISHIHARA†,StudentMemberandHirotoYASUURA†,MemberSUMMARYInthispaper,anovelapplicat
2、ionspecificpowerwhichresultsintheneedforimplementationonpro-optimizationtechniqueutilizingsmallinstructionROMwhichisgrammablehardwareplatform.Currentsemiconduc-placedbetweenaninstructioncacheoramainprogrammemorytortechnologyallowstheintegrationofprocessorco
3、resandCPUcoreisproposed.Ouroptimizationtechniquetargetsembeddedsystemswhichassumethefollowing:(i)instructionandmemorymodulesonasingledie,whichenablesmemoriesareorganizedbytwoon-chipmemories,amainpro-theimplementationofasystemonasinglechip.Con-grammemoryand
4、asubprogrammemory,(ii)thesetwomemoriessequently,thedesignproductivityalongwiththetradi-canbeindependentlypowered-uporpowered-downbyaspecialtionalsynthesisprocesshasnotfollowedtheexponen-instructionofacoreprocessor,and(iii)acompileroptimizesantialgrowthofbo
5、thapplicationsandimplementationallocationofobjectcodeintothesetwomemoriessoastomin-imizeaverageofreadenergyconsumption.Inmanyapplicationtechnology.Theshrinkedtime-to-marketwindowhasprograms,onlyafewbasicblocksarefrequentlyexecuted.There-madethissituationwo
6、rse.Thereisawideconsensusfore,allocatingthesefrequentlyexecutedbasicblocksintolowthatonlyareuseofhighlyoptimizedcorescanmatchpowersubprogrammemoryleadssignificantenergyreduction.thedemandsofthependingapplicationsandthepo-OurexperimentswithactualROM(ReadOnly
7、Memory)mod-ulescreatedwith0.5µmCMOSprocesstechnology,andMPEG2tentialultralargescaleintegration.Therefore,alowcodecprogramdemonstratesignificantenergyreductionsuptopowercore-basedsystem-on-chip,consistingofeasilymorethan50%atbestcaseoverthepreviousapproachth
8、atap-reconfigurablecoresattractsmuchinterestofallsiliconpliesonlydividedbitandwordlinesstructure.vendors.keywords:lowpowerdesign,hardware/softwarecodesign,Inthispaper,weproposeanapplicationspecificmemory,embedd