verilogHDL分频器(奇数分频和偶数分频)

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1、moduleclk_div(//-----------input-----------iCLK,div,//-----------output----------oCLK);//-----------input-----------parameterWIDE=14;inputiCLK;input[WIDE-1:0]div;//-----------output-----------outputoCLK;wireoCLK_odd;wireoCLK_even;assignoCLK=div[0]?oCLK_odd:oCLK_even;div_oddDUTo(

2、.iCLK(iCLK),.oCLK(oCLK_odd),.div(div));div_evenDUTe(.iCLK(iCLK),.oCLK(oCLK_even),.div(div));endmodule//oddmodulediv_odd(//--------input--------iCLK,div,//--------output--------oCLK);//--------input--------parameterWIDE=14;inputiCLK;input[WIDE-1:0]div;//--------output--------outp

3、utoCLK;regoutCLK;/*===========================solve1===========================regcout;reg[WIDE-1:0]cnt;initialcnt=0;wireinCLK;regcc;initialcc=0;always@(posedgecout)cc<=~cc;assigninCLK=iCLK^cc;always@(posedgeinCLK)beginif(cnt<(div[WIDE-1:1]))begincnt<=cnt+1;cout<=1'b0;endelsebeg

4、incnt<=0;cout<=1'b1;endendalways@(negedgeiCLK)outCLK<=cout;assignoCLK=cc;*///========================//solve2//========================reg[WIDE-1:0]cnt_a;initialcnt_a=0;reg[WIDE-1:0]cnt_b;initialcnt_b=0;regcout_a;regcout_b;always@(negedgeiCLK)beginelseif(cnt_a<=(div[WIDE-1:1]))b

5、egincnt_a=cnt_a+1;cout_a=1'b1;endelseif(cnt_a>(div[WIDE-1:1])&&cnt_a<(div[WIDE-1:0]-1))begincout_a=1'b0;cnt_a=cnt_a+1;endelsebegincnt_a=0;endendalways@(posedgeiCLK)beginif(cnt_b<=(div[WIDE-1:1]))begincnt_b=cnt_b+1;cout_b=1'b1;endelseif(cnt_b>(div[WIDE-1:1])&&cnt_b<(div[WIDE-1:0]

6、-1))begincout_b=1'b0;cnt_b=cnt_b+1;endelsebegincnt_b=0;endendassignoCLK=cout_a&cout_b;endmodule//evenmodulediv_even(//--------input--------iCLK,div,//--------output--------oCLK);//--------input--------parameterWIDE=14;inputiCLK;input[WIDE-1:0]div;//--------output--------outputoC

7、LK;regoCLK;initialoCLK=1'b0;reg[WIDE-1:0]cnt;initialoCLK=0;always@(posedgeiCLK)beginif(cnt<(div[WIDE-1:1]-1))cnt<=cnt+1;elsebegincnt<=0;oCLK<=~oCLK;endendendmodule//============================//testbench//============================/*moduleclk_div_test;//-----------input------

8、-----parameterWIDE=14;regiCLK;reg[WIDE-1:0]div;