FPGA VHDL串口

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1、时钟4分频，freqd_dff.vhd文件clk_in：时钟输入clk_out：时钟输出----------------------------------------------------------------------------------------------------------------------libraryieee;useieee.std_logic_1164.all;libraryaltera;usealtera.maxplus2.all;entityfreqd_dffisgeneric(n:integer:=2);port(clk_in:instd_logic

2、;clk_out:outstd_logic);endfreqd_dff;architecturefreqd_dff_archoffreqd_dffissignalq:std_logic_vector(0ton);beginq(0)<=clk_in;G1:foriin0to(n-1)generateUx:dffportmap(notq(i+1),q(i),'1','1',q(i+1));endgenerate;clk_out<=q(n);endfreqd_dff_arch;--------------------------------------------------------------

3、--------------------------------------------------------波特率产生，clock.vhd文件clk:50m时钟clk_out:4倍的波特率时钟sel:波特率选择端，可接拨动开关。00:1200的波特率01:960010:3840011:115200的波特率----------------------------------------------------------------------------------------------------------------------libraryieee;useieee.std_log

4、ic_1164.all;useieee.std_logic_unsigned.all;libraryaltera;usealtera.maxplus2.all;entityclockisport(clk:instd_logic;clk_out:outstd_logic;sel:instd_logic_vector(1downto0));endclock;architectureclock_archofclockissignalcount:std_logic_vector(31downto0);constantstep96:integer:=3298535;--3298535：9600；cons

5、tantstep11:integer:=39582419;--115200；constantstep12:integer:=412317;--1200;constantstep38:integer:=13194139;--38400;signalstep:integer;beginstep<=step12whensel="00"elsestep96whensel="01"elsestep38whensel="10"elsestep11;process(clk)beginifrising_edge(clk)thencount<=count+step;endif;endprocess;clk_ou

6、t<=count(31);endclock_arch;串口接收，recvive.vhd文件clk:4倍的波特率时钟reset:复位端，低电平’0’复位rx:串口rxrx_done:接收完成，1时完成接收rx_buf:接收的数据---------------------------------------------------------------------------------------------------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;

7、useieee.std_logic_arith.all;entityrecviveisgeneric(framlent:integer:=8);Port(clk,reset:std_logic;rxbuf:outstd_logic_vector(7downto0);rx:instd_logic;rx_done:outstd_logic);endrecvive;architecturebehaveo