EDA基于VHDL的乐曲播放电路设计报告

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1、乐曲播放电路设计乐曲播放电路顶层电路图二、模块和源程序1、分频模块分频顶层电路libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityyourname_divisport(clk50mhz:instd_logic;clk5mhz:bufferstd_logic;clk1khz:outstd_logic);endentity;architecturebehavofyourname_divissignalclk50khz:std

2、_logic;beginprocess(clk50mhz)variablecnt:integerrange0to9;beginif(clk50mhz'eventandclk50mhz='1')thenifcnt<9thencnt:=cnt+1;clk5mhz<='0';elsecnt:=0;clk5mhz<='1';endif;endif;endprocess;process(clk5mhz)variablecnt1:integerrange0to99;beginif(clk5mhz'eventandclk5mhz='1')thenifcnt1<99thencnt1:=cn

3、t1+1;clk50khz<='0';elsecnt1:=0;clk50khz<='1';endif;endif;endprocess;process(clk50khz)variablecnt2:integerrange0to49;beginif(clk50khz'eventandclk50khz='1')thenifcnt2<49thencnt2:=cnt2+1;clk1khz<='0';elsecnt2:=0;clk1khz<='1';endif;endif;endprocess;endbehav;libraryieee;useieee.std_logic_1164.a

4、ll;useieee.std_logic_unsigned.all;entityyourname_div2isport(clk:instd_logic;q:outstd_logic);endyourname_div2;architecturertlofyourname_div2isbeginprocess(clk)variablecnt:std_logic_vector(0downto0);beginifclk'eventandclk='1'thenifcnt<1thencnt:=cnt+1;elsecnt:=(others=>'0');endif;endif;ifcnt=

5、1thenq<='1';elseq<='0';endif;endprocess;endrtl;2、music_tone模块libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityyournamemusic_toneisport(cs:instd_logic;index:instd_logic_vector(3downto0);code:outstd_logic_vector(3downto0);high:outstd_log

6、ic_vector(3downto0);tone:outstd_logic_vector(10downto0));endentity;architectureoneofyournamemusic_toneissignalindex1:integerrange0to15;signaltone1:integerrange0to2047;signalcode1:integerrange0to15;beginindex1<=conv_integer(index);tone<=conv_std_logic_vector(tone1,11);code<=conv_std_logic_v

7、ector(code1,4);searh:process(index)beginifcs='0'thencaseindex1iswhen0=>tone1<=2047;code1<=0;high<="0000";when1=>tone1<=773;code1<=1;high<="0000";when2=>tone1<=912;code1<=2;high<="0000";when3=>tone1<=1036;code1<=3;high<="0000";when4=>tone1<=1092;code1<=4;high<=