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Wayne Wolf-Modern VLSI Design_ IP-Based Design -Prentice Hall (2008)

'Wayne Wolf-Modern VLSI Design_ IP-Based Design -Prentice Hall (2008)'
Table of Contents Copyright. 1 Prentice Hall Modern Semiconductor Design Series. 4 Preface to the Fourth Edition 5 Preface to the Third Edition 7 Preface to the Second Edition. 8 Preface 9 About the Author. 12 Chapter 1. Digital Systems and VLSI 13 Section 1.1. Why Design Integrated Circuits?. 15 Section 1.2. Integrated Circuit Manufacturing 17 Section 1.3. CMOS Technology. 30 Section 1.4. Integrated Circuit Design Techniques 33 Section 1.5. IP-Based Design. 45 Section 1.6. A Look into the Future 52 Section 1.7. Summary 53 Section 1.8. References 54 Section 1.9. Problems 54 Chapter 2. Fabrication and Devices. 55 Section 2.1. Introduction. 57 Section 2.2. Fabrication Processes 57 Section 2.3. Transistors 64 Section 2.4. Wires and Vias 86 Section 2.5. Fabrication Theory and Practice. 96 Section 2.6. Reliability. 110 Section 2.7. Layout Design and Tools 115 Section 2.8. References 131 Section 2.9. Problems 132 Chapter 3. Logic Gates. 135 Section 3.1. Introduction. 137 Section 3.2. Combinational Logic Functions 137 Section 3.3. Static Complementary Gates. 140 Section 3.4. Switch Logic. 169 Section 3.5. Alternative Gate Circuits 171 Section 3.6. Low-Power Gates. 181 Section 3.7. Delay through Resistive Interconnect. 187 Section 3.8. Delay through Inductive Interconnect. 199 Section 3.9. Design-for-Yield 205 Section 3.10. Gates as IP. 207 Section 3.11. References 210 Section 3.12. Problems. 211 Chapter 4. Combinational Logic Networks. 217 Section 4.1. Introduction. 219 Section 4.2. Standard Cell-Based Layout 219 Section 4.3. Combinational Network Delay 231 Section 4.4. Logic and Interconnect Design. 247 Section 4.5. Power Optimization 258 Section 4.6. Switch Logic Networks. 263 Section 4.7. Combinational Logic Testing 267 Section 4.8. References. 274 Section 4.9. Problems 274 Chapter 5. Sequential Machines 279 Section 5.1. Introduction. 281 Modern VLSI Design: IP-Based Design, Fourth Edition Section 5.2. Latches and Flip-Flops 281 Section 5.3. Sequential Systems and Clocking Disciplines 293 Section 5.4. Performance Analysis. 304 Section 5.5. Clock Generation. 322 Section 5.6. Sequential System Design. 324 Section 5.7. Power Optimization. 341 Section 5.8. Design Validation 342 Section 5.9. Sequential Testing. 344 Section 5.10. References. 352 Section 5.11. Problems. 352 Chapter 6. Subsystem Design. 357 Section 6.1. Introduction. 359 Section 6.2. Combinational Shifters. 361 Section 6.3. Adders. 364 Section 6.4. ALUs 372 Section 6.5. Multipliers. 372 Section 6.6. High-Density Memory 381 Section 6.7. Image Sensors. 394 Section 6.8. Field-Programmable Gate Arrays. 397 Section 6.9. Programmable Logic Arrays. 399 Section 6.10. Buses and Networks-on-Chips. 403 Section 6.11. Data Paths 427 Section 6.12. Subsystems as IP. 429 Section 6.13. References. 434 Section 6.14. Problems 434 Chapter 7. Floorplanning. 437 Section 7.1. Introduction. 439 Section 7.2. Floorplanning Methods 439 Section 7.3. Global Interconnect. 451 Section 7.4. Floorplan Design. 462 Section 7
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