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1、第四章SoC架构设计及ESL设计OutlinesSystemdesignCommonlyusedcoresandbusesWhat&WhyESLdesignESLdesignMethodologyESLdesignstagesTransactionLevelModelingandstandardWhatESLdesigntooldoSummaryExampleofHardwareSystemArchitectureSource:ARMLtd.SoCdesignincludesSystemarchitecturedesignSoftwarestructuredesignH
2、ardwaredesign(chipdesign)KeysystemArchitectureQuestionsApplicationanalysisWhichprocessorshouldIchoose?Hardware/SoftwarepartitioningWhatisinhardware,whatisinsoftware?BusandmemoryarchitectureHowdoIimplementthecontrolstream?HowdoIimplementthedatastream?CommonlyUsedCores&DSPsARM（AdvancedRISC
3、Machines)RISCarchitectureARM7,ARM9,ARM10,ARM11MIPS(Microprocessorwithoutinterlockedpipedstages)RISCarchitectureMIPS32,MIPS64PowerPC(DevelopedbyIBM、Motorola、Apple)TI’sDSPTMS320C54,TMS320C55,TMS320C62,TMS320C64ADI’sDSPADSP-21,SHARC,TigerSHARC,BlackfinFreescale’sDSPDSP56300,StarCoreCommonly
4、UsedBusesARM’sAMBACommonlyUsedBuses–cont.IBM’sCoreConnectCommonlyUsedBuses–cont.Silicore’sWishbone4kindofinterconnections:Point-to-point,dataflow,sharedbus,crossbarswitchOCP(OpenCoreProtocol)BusAvalonBusDevelopedbyAlteraforNioscoreonFPGAMulti-processorSoC(MPSoC)TI’sDaVinci:ARM+DSPBlockdi
5、agramofTMS320DM6446/3formultimediaapplicationSource:TIMPSoC–cont.TI’sDaVinci:SourcesharingandcommunicationbetweentwocoresSource:TIOutlinesSystemdesignCommonlyusedcoresandbusesWhat&WhyESLdesignESLdesignMethodologyESLdesignstagesTransactionLevelModelingandstandardWhatESLdesigntooldoSummary
6、SystemlevelDesignChallengesHowdoIunderstandperformanceofkeyIPblocksbeforedesigning?System-on-ChipdoesnotmeantosimplyputIPintoachipHowtobuildanoptimizedsystem?Asystemmeanssoftware+hardwareComplexityDriveESLDesign90nmSoCTwoorthreeofmicroprocessorsandmoreDSPsConsiderablymorememoryMorecomple
7、xcommunicationprotocolsSoftwareDriveESLSolution2006StateofEmbeddedMarketSurvey:“themajorityofembeddeddesignprojectsarerunningbehindscheduleorhavebeencancelled”Twentyyearsago,thetypicalembeddeddeviceprobablyran10,000to15,000linesofsoftwarecode;thesedays,twoorthreemillionli
