VHDL例程代码

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1、【例3-1】2选1多路选择器程序。（P31）LIBRARYIEEE;--IEEE库使用说明语句USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21IS--实体说明部分PORT(a,b:INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREmux21aOFmux21IS--结构体说明部分BEGINPROCESS(a,b,s)BEGINIFs='0'THENy<=a;ELSEy<=b;ENDIF;ENDPROCESS;ENDARCHIT

2、ECTUREmux21a;【例3-2】有类属说明的2输入与非门的实体描述。（P33）ENTITYnand2ISGENERIC(t_rise:TIME:=2ns;t_fall:TIME:=1ns)PORT(a:INBIT;b:INBIT;s:OUTBIT);ENDENTITYnand2;【例3-3】n输入与非门的实体描述：（P33）ENTITYnand_nISGENERIC(n:INTEGER);PORT(a:INSTD_LOGIC_VECTOR(n-1DOWNTO0);s:OUTSTD_LOGIC);ENDENTITYnand_n;例3-

3、4】半加器的完整VHDL描述，其中x、y为加数与被加数，s为和信号，c为进位信号。（P36）ENTITYhalf_adderISPORT(x,y:INBIT;s:INBIT;c:OUTBIT);ENDENTITYhalf_adder;ARCHITECTUREdataflowOFhalf_adderISBEGINs<=xXORy;c<=xANDy;ENDARCHITECTUREdataflow;【例3-5】2选1多路选择器的行为描述程序。（P37）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmu

4、x21ISPORT(a,b:INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREbehavOFmux21ISBEGINPROCESS(a,b,s)BEGINIFs='0'THENy<=a;ELSEy<=b;ENDIF;ENDPROCESS;ENDARCHITECTUREbehav;【例3-6】2选1多路选择器数据流描述程序。（P36）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISPORT(a,b:

5、INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREdataflowOFmux21ISBEGINy<=(aAND(NOTs))OR(bANDs);ENDARCHITECTUREdataflow;【例3-7】2选1多路选择器结构描述程序。（P37）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYand21ISPORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDENTITYand21;

6、ARCHITECTUREoneOFand21ISBEGINq<=i0ANDi1;ENDARCHITECTUREone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor21ISPORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDENTITYor21;ARCHITECTUREoneOFor21ISBEGINq<=i0ORi1;ENDARCHITECTUREone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYinv21IS

7、PORT(i0:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDENTITYinv21;ARCHITECTUREoneOFinv21ISBEGINq<=(NOTi0);ENDARCHITECTUREone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISPORT(a,b:INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREstructOFmux21ISCOMPONENTand21POR

8、T(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor21PORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LO