先进芯片封装知识介绍.ppt

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1、AdvancedPackagingTechOutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackagePackageDevelopmentTrendSOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrendCSPFamilyMemoryCardSiPModulePackageDevelopmentTrend3DPackage3DPackage3DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape

2、-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP3S-CSPS-etCSPetCSP+S-CSPPS-fcCSP+SCSPPoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP5SCSPSS-SCSP

3、(paste)UltrathinStackD2D3D4D2D2D3D4D2PoPQFN4SS-SCSPStackedDieTopdieBottomdieFOWmaterilWireTSVTSV(ThroughSiliconVia)Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits

4、. A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace.Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“i

5、nterposer”layerbetweenthechips.Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSVWhat’sPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybyde

6、vicemanufacturerorsubcon.PoPPoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnologyPoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardle

7、velreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkor’sTMV™PoPTopviewBottomviewThroughMoldViaPoPBallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)La

8、serdr