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1、Verilog代码modulealarm_block(inputwirerst,clk,hrs,mins,alarm,outputwire[4:0]alarm_hr,outputwire[5:0]alarm_min);wirehour_s,min_s;alarm_countercounter1(rst,hour_s,min_s,clk,alarm_hr,alarm_min);state_machinealarm_state(rst,alarm,hrs,mins,clk,hour_s,min_s);endmodulemodulestate_machine(inputw
2、irerst,alarm,hrs,mins,clk,outputreghrs_out,mins_out);parameterIDLE=2'b00,SET_HRS=2'b01,SET_MINS=2'b11;reg[1:0]state,next;always@(posedgeclkorposedgerst)if(rst)state<=IDLE;elsestate<=next;always@(alarmorhrsorminsorstate)case(state)IDLE:if(!alarm)beginnext=IDLE;hrs_out=0;mins_out=0;endel
3、seif(alarm&hrs&!mins)beginnext=SET_HRS;hrs_out=1;mins_out=0;endelseif(alarm&!hrs&mins)beginnext=SET_MINS;hrs_out=0;mins_out=1;endSET_HRS:beginif(alarm&hrs&!mins)beginnext=SET_HRS;hrs_out=1;endelsebeginnext=IDLE;hrs_out=0;endmins_out=0;endSET_MINS:beginif(alarm&!hrs&mins)beginnext=SET_M
4、INS;mins_out=1;endelsebeginnext=IDLE;mins_out=0;endhrs_out=0;enddefault:beginnext=2'bx;hrs_out=1'bx;mins_out=1'bx;endendcaseendmodulemodulealarm_counter(inputwirerst,hr_set,min_set,clk,outputreg[4:0]hrs,outputreg[5:0]mins);//setalarmminutesalways@(posedgeclkorposedgerst)if(rst)mins<=0;
5、elseif(min_set&!hr_set)if(mins==6'b111011)mins<=6'b0;elsemins<=mins+6'b000001;//setalarmhoursalways@(posedgeclkorposedgerst)if(rst)hrs<=0;elseif(hr_set&!min_set)if(hrs==5'b10111)hrs<=5'b0;elsehrs<=hrs+5'b00001;endmodulemoduleAlarm_sm_2(inputwirerst,clk,compare_in,toggle_on,outputregrin
6、g);parameterIDLE=1'b0,ACTI=1'b1;regstate,next;always@(posedgeclkorposedgerst)if(rst)state<=IDLE;elsestate<=next;always@(stateorcompare_inortoggle_on)case(state)IDLE:if(toggle_on&compare_in)beginnext<=ACTI;ring<=1;endelsebeginnext<=IDLE;ring<=0;endACTI:if(toggle_on)beginnext<=ACTI;ring<
7、=1;endelsebeginnext<=IDLE;ring<=0;enddefault:beginnext<=1'bx;ring<=1'bx;endendcaseendmodulemodulecomparator(inputwire[4:0]alarm_hr,time_hr,inputwire[5:0]alarm_min,time_min,outputregcompare_out);always@(*)if((alarm_hr==time_hr)&&(alarm_min==time_min))compare_out=1;elsecompare_out=0;en
