设计实例课件.ppt

《设计实例课件.ppt》由会员上传分享，免费在线阅读，更多相关内容在教育资源-天天文库。

1、第四章基本逻辑电路设计实例组合逻辑电路设计时序逻辑电路设计存储器设计状态机设计一、4选1多路选择器四选一yabcds0s1组合逻辑电路的设计LIBRARYIEEE;USEIEEE.std_logic_1164.all;ENTITYmux4ISPORT(a,b,c,d,s0,s1:INstd_logic;y:OUTstd_logic);ENDmux4;ARCHITECTUREfuncOFmux4ISVARIABLEsel:std_logic_vector(1DOWNTO0)；BEGINsel<=s1&s0;y<=aWHENsel=‘00'ELSEbWHENsel=‘0

2、1’ELSEcWHENsel=‘10’ELSEdWHENsel=‘11’ELSE‘X’;ENDfunc;PROCESS(s0，s1)sel:=s1＆s0CASEselISWHEN‘00’=>y<=‘a’；WHEN‘01’=>y<=‘b’；WHEN‘10’=>y<=‘c’；WHEN‘11’=>y<=‘d’；WHENOTHERS=>y<=‘X’；ENDCASE；ENDPROCESS；BEGINPROCESS(s0，s1)BEGINIF(s0=‘0’ands1=‘0’)THENy<=‘a’；ELSIF(s0=‘0’ands1=‘1’)THENy<=‘b’；ELSIF(s0

3、=‘1’ands1=‘0’)THENy<=‘c’；ELSIF(s0=‘1’ands1=‘1’)THENy<=‘d’；ELSEy<=‘X’；ENDIF；ENDPROCESS；二：编码器与译码器1、优先级8-3编码器编码器y0d0d1d2d3d4d5d6d7y1y2优先编码器就是当有两个或两个以上的输入有效时，仅对优先级高的输入进行编码LIBRARYIEEE;USEIEEE.std_logic_1164.all;ENTITYencoder8_3ISPORT(d:INstd_logic_vector(7downto0);y0,y1,y2:OUTstd_logic);END

4、encoder8_3;ARCHITECTUREfuncOFencoder8_3ISBEGINPROCESS(d)VARIABLEtemp:std_logic_vector(2downto0);BEGINIF(d(7)=‘1’)THENtemp:=“111”;ELSIF(d(6)=‘1’)THENtemp:=“110”;ELSIF(d(5)=‘1’)THENtemp:=“101”;ELSIF(d(4)=‘1’)THENtemp:=“100”;ELSIF(d(3)=‘1’)THENtemp:=“011”;ELSIF(d(2)=‘1’)THENtemp:=“010”;EL

5、SIF(d(1)=‘1’)THENtemp:=“001”;ELSIF(d(0)=‘1’)THENtemp:=“000”;ENDIFy(0)<=temp(0);y(1)<=temp(1);y(2)<=temp(2);ENDPROCESSENDfunc;普通8-3编码器CASEdISWHEN‘10000000’=>temp<=‘111’；WHEN‘01000000’=>temp<=‘110’；WHEN‘00100000’=>temp<=‘101’；WHEN‘00010000’=>temp<=‘100’；WHEN‘00001000’=>temp<=‘011’；WHEN‘0

6、0000100’　=>temp<=‘010’；WHEN‘00000010’　=>temp<=‘001’；WHEN‘00000001’　=>temp<=‘000’；WHENOTHERS=>temp<=‘XXX’；ENDCASE；2、138译码器LIBRARYIEEE;USEIEEE.std_logic_1164.all;ENTITYdecoder3_8ISPORT(a2,a1,a0,g1,g2a,g2b:INstd_logic;y:OUTstd_logic_vector);ENDdecoder3_8;ARCHITECTUREfuncOFdecoder3_8ISBEGI

7、NPROCESS(a2,a1,a0,g1,g2a,g2b)VARIABLEtemp:std_logic_vector(2downto0);BEGINtemp:=a2&a1&a0;IF(g1=‘1’andg2a=‘0’andg2b=‘0’)THENCASEtempISWHEN“000”=>y<=“11111110”WHEN“111”=>y<=“01111111”;WHEN“OTHERS”=>y<=“XXXXXXXX”;ENDCASE;ELSEy<=“11111111”ENDIF;ENDPROCESS;ENDfunc;三：加法器1、一位全加器半加器h_adder的描