基于fpga的硬件乘法器设计.doc

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1、libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYmltISPORT(a:INstd_logic_vector(1DOWNTO0);--key1&key2b:INstd_logic_vector(1DOWNTO0);--key3&key4c:OUTstd_logic_vector(7DOWNTO0);--sm_LEDoutputled_bit:OU

2、Tstd_logic);ENDmlt;ARCHITECTUREarchOFmltISSIGNALc_tmp:std_logic_vector(3DOWNTO0);BEGINled_bit<='0';c_tmp<=a*b;PROCESS(c_tmp)BEGINCASEc_tmpISWHEN"0000"=>c<="";WHEN"0001"=>c<="";WHEN"0010"=>c<="";WHEN"0011"=>c<="";WHEN"0100"=>c<="";WHEN"0101"=>c<="";WHEN"0

3、110"=>c<="";WHEN"0111"=>c<="";WHEN"1000"=>c<="";WHEN"1001"=>c<="";WHEN"1010"=>c<="";WHEN"1011"=>c<="";WHEN"1100"=>c<="";WHEN"1101"=>c<="";WHEN"1110"=>c<="";WHEN"1111"=>c<="";WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDarch;