基于简易时钟的设计

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1、简易时钟的设计1.分频电路的设计--实体名：fen100--功能：对输入时钟进行24000分频，得到100Hz信号，--作为数码显示管位扫描信号--接口：clk-时钟输入--qout-100Hz输出信号-------------------------------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityfen100isport(clk:instd_logic;rst:instd

2、_logic;qout:outstd_logic);endfen100;architecturebehaveoffen100isconstantcounter_len:integer:=23999;beginprocess(clk,rst)variablecnt:integerrange0tocounter_len;beginif(rst='0')thencnt:=0;elsifclk'eventandclk='1'thenifcnt=counter_lenthencnt:=0;elsecnt:=cnt+1;endif;casecntiswhen0tocounter_len/2

3、=>qout<='0';whenothers=>qout<='1';endcase;endif;endprocess;endbehave;--实体名：fen1--功能：对输入时钟进行分频，得到1Hz信号--接口：clk-时钟输入--qout-秒输出信号-------------------------------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityfen1isport(cl

4、k:instd_logic;rst:instd_logic;qout:outstd_logic);endfen1;architecturebehaveoffen1isconstantcounter_len:integer:=;beginprocess(clk,rst)variablecnt:integerrange0tocounter_len;beginif(rst='0')thencnt:=0;elsifclk'eventandclk='1'thenifcnt=counter_lenthencnt:=0;elsecnt:=cnt+1;endif;casecntiswhen0t

5、ocounter_len/2=>qout<='0';whenothers=>qout<='1';endcase;endif;endprocess;endbehave;2.60进制--功能：60进制计数器--接口：clk-时钟输入--qout1-个位BCD输出--qout2-十位BCD输出--carry-进位信号输出-------------------------------------------------libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_log

6、ic_arith.all;entityfen60isport(clk:instd_logic;rst:instd_logic;qout1:outstd_logic_vector(3downto0);qout2:outstd_logic_vector(3downto0);carry:outstd_logic);endfen60;architecturebehaveoffen60issignaltem1:std_logic_vector(3downto0);signaltem2:std_logic_vector(3downto0);beginprocess(clk,rst)begi

7、nif(rst='0')thentem1<="0000";tem2<="0000";elsifclk'eventandclk='1'theniftem1="1001"thentem1<="0000";iftem2="0101"thentem2<="0000";carry<='1';elsetem2<=tem2+1;carry<='0';endif;elsetem1<=tem1+1;endif;endif;qout1<=tem1;qout2<=tem2;endprocess;endbehave