模可变计数器的实验报告

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1、南昌大学实验报告学生姓名：学号：专业班级：实验类型：□验证□综合□设计□创新实验日期：实验成绩：实验二模可变计数器的设计（一）实验要求利用控制位M来改变模长要求M=1时模为114计数，M=0时模为16计数；（二）实验步骤1.建立工作库文件夹，输入计数器的VHDL代码并存盘。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYcountISPORT(CLK,M,EN,RST:INSTD_LOGIC;sel0,sel1,sel2:bufferSTD_LOGIC;SG:OUTSTD_LOGIC_

2、VECTOR(7DOWNTO0);--数码管八段CLK1:bufferSTD_LOGIC;GW,SW,BW:bufferSTD_LOGIC_VECTOR(3DOWNTO0);--计数器的个，十，百位COUT:OUTSTD_LOGIC;溢出信号SEL:OUTSTD_LOGIC_VECTOR(7DOWNTO0)--位选信号);ENDcount;ARCHITECTUREbehavOFcountISSIGNALCNT:STD_LOGIC_VECTOR(7DOWNTO0);--数码管分频计数SIGNALJ:STD_LOGIC_VECTOR(11DOWNTO0);--12位BCD计数值SIGNALC

3、NT8:STD_LOGIC_VECTOR(2DOWNTO0);--数码管选择SIGNALA:STD_LOGIC_VECTOR(3DOWNTO0);--数码管显示值0SIGNALMODEL:STD_LOGIC_VECTOR(11DOWNTO0);--模长信号BEGINP1:PROCESS(CLK)--进程P1分出的频率用来数码管的位选扫描BEGINIFCLK'EVENTANDCLK='1'THENCNT<=CNT+1;IFCNT=130THENCLK1<='1';--130分频ELSECLK1<='0';ENDIF;ENDIF;ENDPROCESS;P2:PROCESS(EN,RST,M,

4、CLK1)—计数BEGINCASEMISWHEN'0'=>MODEL<="000000010100";--15WHEN'1'=>MODEL<="000100010100";--115ENDCASE;GW<=J(3downto0);SW<=J(7downto4);BW<=J(11downto8);IFRST='1'THENJ<=(others=>'0');ELSIFCLK1'EVENTANDCLK1='1'THENIFEN='1'THENIFJ

5、F;ELSEJ<=J+1;ENDIF;ELSEJ<=(others=>'0');ENDIF;ENDIF;ENDIF;ENDPROCESS;P3:PROCESS(CLK)--数码管控制BEGINIFCLK'EVENTANDCLK='1'THENIFCNT8<"010"THENCNT8<=CNT8+1;ELSECNT8<=(OTHERS=>'0');ENDIF;ENDIF;SEL(0)<=sel0;SEL(1)<=sel1;SEL(2)<=sel2;CASECNT8IS--个、十、百分别送数码管动态显示WHEN"000"=>sel2<='0';sel1<='1';sel0<='0';A<=G

6、W;WHEN"001"=>sel2<='0';sel1<='0';sel0<='1';A<=SW;WHEN"010"=>sel2<='0';sel1<='0';sel0<='0';A<=BW;WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;P4:PROCESS(A)—七段译码BEGINCASEAISWHEN"0000"=>SG<="00111111";WHEN"0001"=>SG<="00000110";WHEN"0010"=>SG<="01011011";WHEN"0011"=>SG<="01001111";WHEN"0100"=>SG<="01100110";

7、WHEN"0101"=>SG<="01101101";WHEN"0110"=>SG<="01111101";WHEN"0111"=>SG<="00000111";WHEN"1000"=>SG<="01111111";WHEN"1001"=>SG<="01101111";WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;COUT<='1'WHENJ=MODELELSE'0';ENDbehav;2.选目标器件Cyc