eda_常见实例源程序代码vhdl

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1、第4章用VHDL程序实现常用逻辑电路----FileName:fq_divider.vhd----该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率----事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字---------------------------------------------------------------------------LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.

2、ALL;ENTITYfq_dividerISgeneric(n:integer:=60000);PORT(CLK,reset:INSTD_LOGIC;CLK_OUT:bufferSTD_LOGIC);END;ARCHITECTUREAOFfq_dividerISSIGNALCNT1,CNT2:integer:=0;SIGNALOUTTEMP:STD_LOGIC;SIGNALLOUT:STD_LOGIC;SIGNALOUT3:STD_LOGIC:='0';BEGINP1:PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THENIFCNT1=

3、n-1THENCNT1<=0;ELSECNT1<=CNT1+1;ENDIF;ENDIF;ENDPROCESSP1;P2:PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='0'THENIFCNT2=n-1THENCNT2<=0;ELSECNT2<=CNT2+1;ENDIF;ENDIF;ENDPROCESSP2;P3:PROCESS(CNT1,CNT2)BEGINif((nmod2)=1)thenIFCNT1=1THENIFCNT2=0THENOUTTEMP<='1';ELSEOUTTEMP<='0';ENDIF;ELSIFCNT1=(n+1)/2

4、THENIFCNT2=(n+1)/2THENOUTTEMP<='1';ELSEOUTTEMP<='0';ENDIF;ELSEOUTTEMP<='0';ENDIF;elseifcnt1=1thenouttemp<='1';elsif(cnt1=(n/2+1))thenouttemp<='1';elseouttemp<='0';endif;endif;ENDPROCESSP3;P4:PROCESS(OUTTEMP,clk,reset)BEGINifreset='0'thenclk_out<=clk;elsif((n/=2)and(n/=1))thenIFOUTTEMP'

5、EVENTANDOUTTEMP='1'THENCLK_OUT<=NOTCLK_OUT;ENDIF;elsif(n=2)thenif(clk'eventandclk='1')thenclk_out<=notclk_out;endif;elseclk_out<=clk;endif;ENDPROCESSP4;ENDA;4.1组合逻辑电路设计4.1.1基本逻辑门libraryieee;useiee.std_logic_1164.all;entityjbmisport(a,b:inbit;f1,f2,f3,f4,f5,f:outbit);endjbm;architecture

6、aofjbmisbeginf1<=aandb;--构成与门f2<=aorb;--构成或门f<=nota;--构成非门f3<=anandb;--构成与非门f4<=anorb;--构成异或门f5<=not(axorb);--构成异或非门即同门end;4.1.2三态门libraryieee;useieee.std_logic_1164.all;entitytri_sisport(enable:instd_logic;datain:instd_logic_vector(7downto0);dataout:outstd_logic_vector(7downto0));endt

7、ri_s;architecturebhvoftri_sisbeginprocess(enable,datain)beginifenable='1'thendataout<=datain;elsedataout<="ZZZZZZZZ";endif;endprocess;endbhv;4.1.33-8译码器libraryieee;useieee.std_logic_1164.all;entitydecoder3_8isport(a,b,c,g1,g2a,g2b:instd_logic;y:outstd_logic_vector(7downto0));enddecod