用vhdl描述下列器件的功能

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1、1．用VHDL描述下列器件的功能（1）集成移位寄存器74194（2）集成计数器74161（1）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYS_R74194ISPORT(clrn,clk,slsi,srsi:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);ss:INSTD_LOGIC_VECTOR(1DOWNTO0);q:OUTSTD_LOGIC_VECTOR(3DO

2、WNTO0));ENDS_R74194;ARCHITECTUREbhvOFS_R74194ISSIGNALtmp:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk,clrn)BEGINIF(clrn='0')THENtmp<="0000";ELSIF(clk'EVENTANDclk='1')THENIF(ss="11")THENtmp<=din;ELSIF(ss="01")THENtmp<=srsi&tmp(3downto1);ELSIF(ss="10")THENtmp<=t

3、mp(2downto0)&slsi;ENDIF;ENDIF;q<=tmp;ENDPROCESS;ENDbhv;（2）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYS_C74161ISPORT(clk,ldn,clrn,enp,ent:INSTD_LOGIC;din:INSTD_LOGIC_VECTOR(3DOWNTO0);q:OUTSTD_LOGIC_VECTOR(3DOWNTO0);rco:OUTSTD_L

4、OGIC);ENDS_C74161;ARCHITECTUREbehavOFS_C74161ISSIGNALtmp:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk,clrn)BEGINIFclrn='0'THENtmp<="0000";ELSIF(clk'EVENTANDclk='1')THENIFldn='0'THENtmp<=din;ELSIF(enp='1'andent='1')THENtmp<=tmp+1;ENDIF;ENDIF;q<=tmp;ENDPROCESS;r

5、co<=tmp(3)andtmp(2)andtmp(1)andtmp(0)andent;ENDbehav;2.试给出一位全减器的算法描述、数据流描述、结构描述和混合描述（1）算法描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYf_subISPORT(x,y,sub_in:INSTD_LOGIC;sub_out,diff:OUTSTD_LOGIC);ENDf_sub;ARCHITECTUREbhvOFf_sub

6、ISSIGNALtmp:STD_LOGIC_VECTOR(2DOWNTO0);BEGINtmp<=x&y&sub_in;PROCESS(tmp)BEGINCASEtmpISWHEN"000"=>diff<='0';sub_out<='0';WHEN"001"=>diff<='1';sub_out<='1';WHEN"010"=>diff<='1';sub_out<='1';WHEN"011"=>diff<='0';sub_out<='1';WHEN"100"=>diff<='1';sub_out<='0';WHE

7、N"101"=>diff<='0';sub_out<='0';WHEN"110"=>diff<='0';sub_out<='0';WHEN"111"=>diff<='1';sub_out<='1';WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDbhv；（2）数据流描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALLENTITYf_subISPORT(x,y,sub_in:INSTD_LOGIC

8、;sub_out,diff:OUTSTD_LOGIC);ENDf_sub;ARCHITECTURErtlOFf_subISBEGINdiff<=xXORyXORsub_in;sub_out<=(NOTxANDy)OR((xXNORy)ANDsub_in);ENDrtl;（3）结构描述--半加器描述LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL