资源描述：
《Xilinx FPGA普通IO作PLL时钟输入.doc》由会员上传分享，免费在线阅读，更多相关内容在应用文档-天天文库。
1、XilinxFPGA普通IO作PLL时钟输入 在xilinxZC7020的片子上做的实验; [结论] 普通IO不能直接作PLL的时钟输入,专用时钟管脚可以; 普通IO可以通过BUFG再连到PLL的时钟输入上,但要修改PLL的设置inputclk的选项中要选择”NoBuffer”; 具体内部布局分配可以通过Xilinx的FPGAEditor来查看, ZYNQ的时钟管理也和之前的片子略有不同,之后在另一篇介绍,相关文档 [Demo1]//demo1twobufgconnect moduleiobuf( inputclk, inputrst, outputled
2、); wireclkin_w; BUFGBUFG_inst( .O(clkin_w),//Clockbufferoutput .I(clk)//Clockbufferinput ); pll0u_pll0( .CLK_IN1(clkin_w),//IN .CLK_OUT1(clkout),//OUT .RESET(rst));//IN assignled=clkout; endmodule 锁相环PLL默认输入前端有个BUFG单元,而两个BUFG不能相连,所以会报这样的错: ERROR:NgdBuild:770-IBUFG‘u_pll0/clkin1_bu
3、f’andBUFG‘BUFG_inst’onnet ’clkin_w’arelinedupinseries.BuffersofthesamedirecTIoncannotbe placedinseries. ERROR:NgdBuild:924-inputpadnet‘clkin_w’isdrivingnon-bufferprimiTIves: [Demo2] //demo2regulariodirectlyconnecttoPLL moduleiobuf( inputclk, inputrst, outputled );wireclkin_w; /* BU
4、FGBUFG_inst( .O(clkin_w),//Clockbufferoutput .I(clk)//Clockbufferinput ); */ pll0u_pll0( .CLK_IN1(clk),//IN .CLK_OUT1(clkout),//OUT .RESET(rst));//IN assignled=clkout; endmodule 普通IO不能直接做锁相环的输入,所以会报这样的错: ERROR:Place:1397-AclockIOB/MMCMclockcomponentpairhavebeenfoundthat arenotplac
5、edatanopTImalclockIOB/MMCMsitepair.TheclockIOB componentisplacedatsite.ThecorrespondingMMCMcomponent isplacedatsite.TheclockIOcan usethefastpathbetweentheIOBandtheMMCMiftheIOBisplacedona ClockCapableIOBsitethathasdedicatedfastpathtoMMCMsiteswithinthe sameclockregion.Youmaywanttoanalyzewhy
6、thisproblemexistsand correctit.IfthissubopTImalconditionisacceptableforthisdesign,you mayusetheCLOCK_DEDICATED_ROUTEconstraintinthe.ucffiletodemotethis messagetoaWARNINGandallowyourdesigntocontinue.However,theuseof thisoverrideishighlydiscouragedasitmayleadtoverypoortiming results.Itisrec
7、ommendedthatthiserrorconditionbecorrectedinthe design.AlistofalltheCOMP.PINsusedinthisclockplacementruleis ERROR:Pack:1654-Thetiming-drivenplacementphaseencounteredanerror. 如果有ucf中加上这句约束: NETclkCLOCK_DEDICATED_ROUTE=FALSE; 依旧会报错,在Z
