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1、278IEEETRANSACTIONSONCOMPUTER-AIDEDDESIGNOFINTEGRATEDCIRCUITSANDSYSTEMS,VOL.26,NO.2,FEBRUARY2007Power-EfficientRAMMappingAlgorithmsforFPGAEmbeddedMemoryBlocksRussellTessier,Member,IEEE,VaughnBetz,Member,IEEE,DavidNeto,AaronEgier,Member,IEEE,andThiagar
2、ajaGopalsamyAbstractContemporaryfield-programmablegatearray(FPGA)designrequiresaspectrumofavailablephysicalresources.AsFPGAlogiccapacityhasgrown,locallyaccessedFPGAembeddedmemoryblockshaveincreasedinimportance.WhentargetingFPGAs,applicationdesignersof
3、tenspecifyhigh-levelmemoryfunctions,whichexhibitarangeofsizesandcontrolstructures.TheselogicalmemoriesmustbemappedtoFPGAembeddedmemoryresourcessuchthatphysicaldesignobjectivesaremet.Inthispaper,asetofpower-efficientlogical-to-physicalRAMmappingalgorit
4、hmsisdescribed,whichconvertsuser-definedmemoryspecificationstoon-chipFPGAmemoryblockresources.ThesealgorithmsminimizeRAMdynamicpowerbyevaluatingarangeofpossibleembeddedmemoryblockmappingsandselectingthemostpower-efficientchoice.Ourautomatedapproachhasbe
5、envalidatedwithbothsimulationofpowerdissipationandmeasurementsofpowerdissipationonFPGAhardware.AcomparisonofmeasuredpowerreductionsFig.1.Coredynamicpowerdistributionfor124benchmarksmappedtotovaluesdeterminedviasimulationconfirmstheaccuracyofStratixIId
6、evices.Testvectorsarenotavailableforthesedesigns;thus,logicoursimulationapproach.Ourpower-awareRAMmappingisassumedtotoggleduring12.5%ofclockcycles.algorithmshavebeenintegratedintoacommercialFPGAcompilerandtestedwith34largeFPGAbenchmarks.Throughbetwee
7、n10%and20%ofcoredynamicpowerintypicalexperimentation,weshowthat,onaverage,embeddedmemoryFPGAdesigns[1].Forexample,Fig.1illustratesthecoredynamicpowercanbereducedby26%andoverallcoredynamicpowercanbereducedby6%withaminimalloss(1%)indesigndynamicpowerbr
8、eakdownfor124FPGAdesignsofvaryingperformance.Inaddition,itisshownthattheavailabilityofsizesandfunctionalitiesmappedtoAlteraStratixII[2]devices.multipleembeddedmemoryblocksizesinanFPGAreducesOnaverage,embeddedmemoryconsumesasmuchpowerasembeddedmemoryd