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1、ClockandDataRecoveryCircuitAttheoutputofthelimitingamplifier,theamplifieddatasignalwithsharpeneddataedgesisavailableforfurtherprocessing,butuniqueinterpretationofthereceivedsignalrequirestiminginformation.Serialcommunicationlinksdonotprovideasynchronizationsignalonaseparatechannelandthe
2、reforethereceivermustrelyontheextractionofthetiminginformationfromthedatastream.Thisclockanddatarecoveryprocesscanbeperformedinasimilarmannerinopticalcommunication,electricalseriallinks,harddriveread-outchannels,aswellasinsomememoryinterfaces.Inthelatterfield,advocatesandopponentsofthec
3、lockforwardingschemestilldebateabouttheadvantagesanddrawbacksofper-channelclockrecoverycircuits.Properdenominationofthewholesynchronizationprocesswouldbeclockrecoveryanddataretiming,betterdescribingthebehaviorallyindependentoperations.Indeedtherecoveredclockisusedtore-sampletheincoming(
4、orsometimesdelayed)datatoprovidepropertiminginformation,i.e.synchronicity,forthefollowingblocks(Figure8.1).However,inmanyimplementations,theretimingoperationisembeddedintheclockrecoveryparttoachieveimprovedcircuitperformance.FIGURE8.1.ClockrecoveryanddataretimingprincipleThemajorchallen
5、gesofmultichannelclockrecoverycircuitdesignhavealreadybeenpresented,namely,theachievementoflow-powerandlow-areaoverheadwithminimumimpactonthecircuitperformance.First,anintroductiontotheimportantconceptsinthedesignofclockrecoverycircuitsispresented.Then,anoverviewofavarietyofclockrecover
6、ytopologieswiththeirrespectiveadvantagesanddrawbacksallowsthereadertofullyunderstandthedesignchoicesoperatedlaterinthischapter.Afterdiscussionof7appropriatetopologiesformultichannelclockrecovery,atop-downdesignapproachispresentedwhichvalidatesthejitterperformanceoftheselectedtopologyatt
7、heconceptlevel,atthebehaviorallevelandatthetransistorlevel.Finally,thetransistor-leveldesignoftheCDRisbrieflydiscussedandcharacterizationtechniquesareintroduced.1.ClockRecoveryPrinciplesHistorically,clockrecoverywasperformedusingresonantfilter-basedstructures,eitherusingdiscret
