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1、Testing3DChipsContainingThrough-SiliconViasErikJanMarinissenYervantZorianIMECvzwVirageLogicKapeldreef7547100BaysideParkwayB-3001LeuvenFremont,CA94538BelgiumUnitedStatesofAmericaerik.jan.marinissen@imec.beyervant.zorian@viragelogic.comnectscanoperateathighers
2、peedsandlowerpowerdissipation.AbstractTSV-based3Dtechnologiesenablethecreationofanewgener-ationofsuperchipsbyopeningupnewarchitecturalopportu-Todaysminiaturizationandperformancerequirementsre-nities[4,5].Hence,theyallowthesemiconductorindustrytosultintheusag
3、eofhigh-densityintegrationandpackagingcontinuetostillitshungerformorefunctionality,bandwidth,technologies,suchas3DStackedICs(3D-SICs)basedonandperformanceatsmallersizes,powerdissipation[6],andThrough-SiliconVias(TSVs).Duetotheiradvancedmanufac-cost;eveninane
4、rainwhichconventionalfeature-sizescalingturingprocessesandphysicalaccesslimitations,thecomplexitybecomesincreasinglydifficultandexpensive.andcostassociatedwithtestingthistypeof3D-SICsareconsideredmajorchallenges.ThisEmbeddedTutorialprovidesLikeallICs,alsothes
5、enewTSV-based3D-SICsneedtobeanoverviewofthemanufacturingstepsofTSV-based3Dchipstestedformanufacturingdefects,inordertoguaranteesufficientandtheirassociatedtestchallenges.Itdiscussesthenecessaryoutgoingproductqualitytothecustomer.InthisEmbeddedTu-flowsforwafer-
6、levelandpackage-leveltests,thechallengestorialpaper,wedescribethetestneedsof3D-SICs,reviewtowithrespecttotestcontentsandwafer-levelprobeaccess,andwhatextentexistingtestsolutionscanbeusedtoaddressthose,theon-chipDfTinfrastructurerequiredfor3D-SICs.anddiscussw
7、hatnewtestchallengescomewiththisnewclassofproducts.Theremainderofthispaperisorganizedasfollows.Section21IntroductionpositionsTSV-based3D-SICsinthemarketplaceanddescribesvariousTSVtechnologyoptions.Testflowsfor2Dand3DICsThesemiconductorindustryisonanongoingque
8、sttointegratearecomparedinSection3.Section4arguesthatmodulartestingmorefunctionalityintoasmallerformfactorwithincreasedper-isaveryappropriateapproachfor3D-SICsandliststherequiredformance,lowerpo