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1、三・VHDL语言设计思路及实现4.VHDL语言实现分频器(十分频)使用两个进程：p1用来控制在时钟上升沿触发，p2用中间变量temp来控制占空比为10%LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYfenpinISPORT(clk,clear:INSTD丄OGIC;clk_out:OUTSTD_LOGIC);ENDfenpin;ARCHITECTUREstrucOFfenpinISSIGNALtemp:INTEGERRANGEOTO11;BEGINp1
2、:PR0CESS(clear,clk)BEGINIFclearsTHENtemp<=0;ELSIFclk'EVENTANDelk二叩THENIFtemp=9THENtemp<=0;ELSEtemp<=temp+1;ENDIF;ENDIF;ENDPROCESSp1;p2:PROCESS(temp)BEGINIFtemp<9THENclk_out<='0';ELSEclk_out<='1';ENDIF;ENDPROCESSp2;ENDstruc;2.VHDL语言实现模10计数器异步复位十进制计数器计数状态为0000-1001状态的改变通过q_temp实现，
3、最后将其赋值给q,进行输出。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;PORT(clk,clr:INSTD丄OGIC;q:OUTSTD_L0GIC_VECT0R(3DOWNTO0));ENDbcd24;ARCHITECTUREstrucOFbcd24ISSIGNALq_temp:STD丄OGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk)BEGINIF(clkfEVENTANDclkM)THENIFclr二'O'THENq_tem
4、p<=,,0000,';ELSIFqJemp^lOOVTHENq_temp<=,,0000";ELSEq_temp<=q_temp+1;ENDIF;ENDIF;ENDPROCESS;q<=q_temp;ENDstruc;2.VHDL语言实现数码显示译码器通过不同的字段编码使LED数码管显示不同数字，用a表示计数状态，b表示字段a~g,下载时将b的7个值对应相应的a~g,以正确显示数字。libraryieee;useieee.std_logic_1164.all;entityyimaqi24isport(a:instd_logic_vector(3dow
5、nto0);b:outstd_logic_vector(6downto0);cat:outstd_logic_vector(5downto0));endyimaqi24;architectureyimaqiofyimaqi24isbeginprocess(a)begincaseaiswhen,,0000,,=>b<=,,1111110n;-0when,,0001,,=>b<=,,0110000n;-1when"0010,,=>b<=,,1101101n;-2whenn0011,'=>b<=,,1111001M;-3when,,0100,,=>b<=,,
6、0110011n;-4when,,0101,,=>b<=,,1011011n;-5whenn0110H=>b<=n1011111n;-6when"0111,,=>b<=,,1110000n;-7whenn1000n=>b<=n1111111n;-8whenH1001,,=>b<=,,1111011n;-9whenothers=>b<="0000000n;endcase;endprocess;catv二end;2.VHDL语言实现数码管0~9自动显示系统由三部分组成：分频系数为50M的分频器，模10计数器，数码管显示译码器。分频器将计算机频率降低作为输入
7、，使数字变化周期为1秒。模10计数器用以控制输出10个数字。数码管显示译码器用来下载至实验板上观察结果。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYshiyan24ISPORT(clk:instd」ogic;clear:instd」ogic;b:outstd_logic_vector(6downto0);cat:outstd_logic_vector(5downto0));ENDshiyan24;ARCHITECTUREaOFshiyan24IS
8、signaltmp:integerrange0to24999999;signalclktmp:
