VHDL基本逻辑电路设计.ppt

《VHDL基本逻辑电路设计.ppt》由会员上传分享，免费在线阅读，更多相关内容在PPT专区-天天文库。

1、第6章基本逻辑电路设计6.1组合逻辑电路设计6.2时序逻辑电路设计6.3存储器习题6.1组合逻辑电路设计6.1.1简单门电路1.2输入“与非”门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnand2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDnand2;ARCHITECTUREnand2_rtlOFnand2ISBEGINy<=aNANDb;--NOT(aANDb)ENDnand2_rtl;ARCHITECTUREn

2、and2_behaveOFnand2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a&b;CASEcombISWHEN“00”=>y<=‘1’;WHEN“01”=>y<=‘1’;WHEN“10”=>y<=‘1’;WHEN“11”=>y<=‘0’;WHENOTHERS=>y<=‘X’;ENDCASE;ENDPROCESS;ENDnand2_behave;数据流描述行为描述2.2输入“或非”门LIBRARYIEE

3、E;USEIEEE.STD_LOGIC_1164.ALL;ENTITYnor2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDnor2;ARCHITECTUREnor2_rtlOFnor2ISBEGINy<=aNORb;--NOT(aORb)ENDnor2_rtl;ARCHITECTUREnor2_behaveOFnand2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a&

4、b;CASEcombISWHEN“00”=>y<=‘1’;WHEN“01”=>y<=‘0’;WHEN“10”=>y<=‘0’;WHEN“11”=>y<=‘0’;WHENOTHERS=>y<=‘X’;ENDCASE;ENDPROCESS;ENDnor2_behave;数据流描述行为描述3.反相器LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYinverterISPORT(a:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDinverter;ARCH

5、ITECTUREinverter_rtlOFinverterISBEGINy<=NOTa;ENDinverter_rtl;ARCHITECTUREinverter_behaveOFinverterISBEGINPROCESS(a)BEGINIF(a=‘1’)THENy<=‘0’;ELSEy<=‘1’;ENDIF;ENDPROCESS;ENDinverter_behave;数据流描述行为描述4.2输入“异或”门LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYxo

6、r2ISPORT(a,b:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDxor2;ARCHITECTURExor2_rtlOFxor2ISBEGINy<=aXORb;ENDxor2_rtl;ARCHITECTURExor_behaveOFxor2ISBEGINPROCESS(a,b)VARIABLEcomb:STD_LOGIC_VECTOR(1DOWNTO0);BEGINcomb:=a&b;CASEcombISWHEN“00”=>y<=‘0’;WHEN“01”=>y<=‘1’;WHEN

7、“10”=>y<=‘1’;WHEN“11”=>y<=‘0’;WHENOTHERS=>y<=‘X’;ENDCASE;ENDPROCESS;ENDxor2_behave;数据流描述行为描述6.1.2编、译码器与选择器1.3-8译码器LIBRARYIEEE；USEIEEE.STD_LOGIC_1164.ALL;ENTITYdecoder3to8ISPORT(a,b,c,g1,g2a,g2b:INSTD_LOGIC;y:outstd_logic_vector(0to7));ENDdecoder3to8;ARC

8、HITECTUREbehaveOFdecoder3to8ISSIGNALindata:STD_LOGIC_VECTOR(2DOWNTO0);BEGINindata<=c&b&a;PROCESS(indata,g1,g2a,g2b)BEGINIF(g1=‘1’ANDg2a=‘0’ANDg2b=‘0’)THENCASEindataISWHEN“000”=>y<=“11111110”;WHEN“001”=>y<=“11111101”;WHEN“010”=>y<