定时器PWM输出实验.pdf

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1、定时器PWM输出实验1.实验目的1)熟悉Linux开发环境。2)掌握S5PV210内部相关寄存器的操作方法，最终实现对外部设备的控制。3)熟悉在Linux裸机环境下的C语言编程。4)熟悉S5PV210的定时器编程。2实验内容学习并编程实现ARM的定时器PWM输出。3实验设备1)硬件：S5PV210教学实验箱、PC机；2)软件：PC机操作系统Windows98(2000、XP)＋VMwareworkstation+Ubuntu12开发环境。4基础知识S5PV210共有5个32bit的PWM定时器，其中定时器0、1、2、3有PWM功能，定时器4没有输出引脚。PWM定时器使用PCLK_PSYS

2、作为时钟源。专业文档供参考，如有帮助请下载。时钟初始化相关寄存器专业文档供参考，如有帮助请下载。专业文档供参考，如有帮助请下载。定时器初始化相关定时器专业文档供参考，如有帮助请下载。专业文档供参考，如有帮助请下载。定时器PWM输出控制的相关内容：GPD0CON确定GPD0DAT引脚的功能，本实验用GPD0[0]作为TOUT_0的输出。实验程序#defineMP0_4CON(*(volatileunsignedlong*)0xE0200340)#defineMP0_4DAT(*(volatileunsignedlong*)0xE0200344)#defineGPD0CON(*(volati

3、leunsignedlong*)0xE02000A0)#defineGPD0DAT(*(volatileunsignedlong*)0xE02000A4)//clock专业文档供参考，如有帮助请下载。#defineAPLL_LOCK(*(volatileunsignedlong*)0xE0100000)#defineMPLL_LOCK(*(volatileunsignedlong*)0xE0100008)#defineAPLL_CON0(*(volatileunsignedlong*)0xE0100100)#defineAPLL_CON1(*(volatileunsignedlong*)

4、0xE0100104)#defineMPLL_CON(*(volatileunsignedlong*)0xE0100108)#defineCLK_SRC0(*(volatileunsignedlong*)0xE0100200)#defineCLK_SRC1(*(volatileunsignedlong*)0xE0100204)#defineCLK_SRC2(*(volatileunsignedlong*)0xE0100208)#defineCLK_SRC3(*(volatileunsignedlong*)0xE010020c)#defineCLK_SRC4(*(volatileunsig

5、nedlong*)0xE0100210)#defineCLK_SRC5(*(volatileunsignedlong*)0xE0100214)#defineCLK_SRC6(*(volatileunsignedlong*)0xE0100218)#defineCLK_SRC_MASK0(*(volatileunsignedlong*)0xE0100280)#defineCLK_SRC_MASK1(*(volatileunsignedlong*)0xE0100284)#defineCLK_DIV0(*(volatileunsignedlong*)0xE0100300)#defineCLK_D

6、IV1(*(volatileunsignedlong*)0xE0100304)#defineCLK_DIV2(*(volatileunsignedlong*)0xE0100308)#defineCLK_DIV3(*(volatileunsignedlong*)0xE010030c)#defineCLK_DIV4(*(volatileunsignedlong*)0xE0100310)#defineCLK_DIV5(*(volatileunsignedlong*)0xE0100314)#defineCLK_DIV6(*(volatileunsignedlong*)0xE0100318)#de

7、fineCLK_DIV7(*(volatileunsignedlong*)0xE010031c)#defineCLK_DIV0_MASK0x7fffffff#defineAPLL_MDIV0x7d#defineAPLL_PDIV0x3#defineAPLL_SDIV0x1#defineMPLL_MDIV0x29b#defineMPLL_PDIV0xc#defineMPLL_SDIV0x1#defineset_pll(mdiv,pdi