2、门的开启和关闭,同时也控制整机逻辑关系。原理框图:数码显示译码器锁存器计数器门闸电路逻辑控制电路时基电路1.时基产生与测频时序控制电路模块:LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCTRLIS PORT (CLK:INSTD_LOGIC;--系统时钟LOCK:OUTSTD_LOGIC;--锁存信号EN:OUTSTD_LOGIC;--计数允许信号CLR:OUTSTD_LOGIC);--清零信号ENDEN
3、TITY;ARCHITECTUREARTOFCTRLISSIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK) BEGIN IF(CLK'EVENTANDCLK='1')THEN IFQ="1111"THEN Q<="0000"; ELSE Q<=Q+1; ENDIF; ENDIF;EN<=NOTQ(3);LOCK<=Q(3)ANDNOT(Q(2))ANDQ(1)
5、CTOR(3DOWNTO0));--计数器输出信号ENDCB10;ARCHITECTUREARTOFCB10IS BEGIN PROCESS(CLK,CLR,EN) BEGIN IFCLR='1'THEN COUNT10<="0000"; ELSIFRISING_EDGE(CLK)THEN IF(EN='1')THEN IFCOUNT