超大CMOS集成电路原理cha.ppt

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1、DigitalIntegratedCircuitsADesignPerspectiveCopingwithInterconnectJanM.RabaeyAnanthaChandrakasanBorivojeNikolicDecember15,2002ImpactofInterconnectParasitics•ReduceRobustness•AffectPerformanceIncreasedelayIncreasepowerdissipationClassesofParasitics•Capacitiv

2、e•Resistive•InductiveINTERCONNECTDealingwithCapacitanceCapacitiveCrossTalkCapacitiveCrossTalkDynamicNode3x1mmoverlap:0.19VdisturbanceCYCXYVDDPDNCLKCLKIn1In2In3YX2.5V0VCapacitiveCrossTalkDrivenNodetXY=RY(CXY+CY)Keeptime-constantsmallerthanrisetimeV(Volt)00

3、.50.450.40.350.30.250.20.150.10.05010.80.6t(nsec)0.40.2XYVXRYCXYCYtr↑DealingwithCapacitiveCrossTalkAvoidfloatingnodesProtectsensitivenodesMakeriseandfalltimesaslargeaspossibleDifferentialsignalingDonotrunwirestogetherforalongdistanceUseshieldingwiresUseshie

4、ldinglayersShieldingGNDGNDShieldingwireSubstrate(GND)ShieldinglayerVDDCrossTalkandPerformanceCc-Whenneighboringlinesswitchinoppositedirectionofvictimline,delayincreasesDELAYDEPENDENTUPONACTIVITYINNEIGHBORINGWIRESMillerEffect-Bothterminalsofcapacitorareswitc

5、hedinoppositedirections(0Vdd,Vdd0)-Effectivevoltageisdoubledandadditionalchargeisneeded(fromQ=CV)ImpactofCrossTalkonDelayrisratiobetweencapacitancetoGNDandtoneighborStructuredPredictableInterconnectExample:DenseWireFabric([SunilKathri])Trade-off:Cross-co

6、uplingcapacitance40xlower,2%delayvariationIncreaseinareaandoverallcapacitanceAlso:FPGAs,VPGAsInterconnectProjectionsLow-kdielectricsBothdelayandpowerarereducedbydroppinginterconnectcapacitanceTypesoflow-kmaterialsinclude:inorganic(SiO2),organic(Polyimides)

7、andaerogels(ultralow-k)ThenumbersbelowareontheconservativesideoftheNRTSroadmapeEncodingDataAvoidsWorst-CaseConditionsEncoderDecoderBusInOutDrivingLargeCapacitancesVinVoutCLVDDTransistorSizingCascadedBuffersUsingCascadedBuffersCL=20pFInOut12N0.25mmprocessC

8、in=2.5fFtp0=30psF=CL/Cin=8000fopt=3.6N=7tp=0.76ns(SeeChapter5)OutputDriverDesignTradeoffPerformanceforAreaandEnergyGiventpmaxfindNandfAreaEnergyDelayasaFunctionofFandN101357NumberofbufferstagesN91110,0