资源描述：
《FPGA程序乘法器》由会员上传分享，免费在线阅读，更多相关内容在教育资源-天天文库。
1、乘法器：byleasualmodulemui44(a,b,rst,out,bai,shi,ge);inputrst;input[3:0]a,b;outputout,bai,shi,ge;reg[3:0]bai,shi,ge;wire[7:0]out1,out2,out3,out4;reg[7:0]out;always@(*)if(!rst)beginout=0;bai=0;shi=0;ge=0;endelsebeginout=out1+out2+out3+out4;bai=out/100;shi=out%100/10;ge=out%10;endassignout1=(b[0]==1)
2、?a:0;assignout2=(b[1]==1)?(a<<1):0;assignout3=(b[2]==1)?(a<<2):0;assignout4=(b[3]==1)?(a<<3):0;endmodule奇数分频：byleasualmodulejishufenp(rst,clk,clkout);parameterN=3;//计数器的位数N的最大计数值要大于或等于MparameterM=7;//要分频的模，取奇数inputrst;inputclk;outputclkout;regtempp,tempn;reg[N-1:0]count;always@(negedgerstorpose
3、dgeclk)if(!rst)begincount<=0;tempp<=0;endelsebegincount<=count+1;if(count==M/2)tempp<=1;elseif(count==M-1)begintempp<=0;count<=0;endendalways@(negedgerstornegedgeclk)if(!rst)tempn<=0;elsetempn<=tempp;assignclkout=tempp
4、tempn;endmodule状态机：/**************************************gongneng:jiancexul
5、ie1011chengxubyleasual2010.11.29**************************************/moduleztj2(a,rst,clk,q);inputclk,a,rst;outputq;regq;reg[7:0]cur_state;parameters1=8'b0000_0001,s2=8'b0000_0010,s3=8'b0000_0100,s4=8'b0000_1000,s5=8'b0001_0000,s6=8'b0010_0000,s7=8'b0100_0000,s8=8'b1000_0000;always@(posedgecl
6、kornegedgerst)if(~rst)begincur_state<=s1;endelsecase(cur_state)s1:begincur_state<=((a==1)?s2:s1);q<=0;ends2:begincur_state<=((a==0)?s3:s2);q<=0;ends3:begincur_state<=((a==1)?s4:s1);q<=0;ends4:begincur_state<=((a==1)?s5:s3);q<=0;ends5:begincur_state<=((a==0)?s6:s2);q<=0;ends6:begincur_state<=((a
7、==1)?s7:s1);q<=0;ends7:begincur_state<=((a==0)?s8:s5);q<=0;ends8:if(a==1)begincur_state<=s1;q<=1;endelsebegincur_state<=s1;q<=0;enddefault:begincur_state<=s1;q<=0;endendcaseendmodule
