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1、实验报告一、实验目的熟悉利用QuartusII的VIIDL文本设计流程，学习基本时序电路的设计、多层次电路设计、编译及仿真全过程。二、实验内容1.设计含异步清零和同步时钟使能的加法计数器。i-aii(1)代码:1LI3RARYIEEE;2USEIEEE・5TD_匸OGTC_1164•盒二二；3USEIEEE・5TD【二OGTC【UNSTGNED•盒二二；4=ENTITYcount~IS一5SFORKclkzclrrenb:INSTD_匸0GIC;6cout:OUT5TD_LOgWc_VECTOR(3DOWI-TTO0));7ENDEN
2、TITYcount;□盒RCHITECTUREo匚<2OFcountIS91011Iz1314151617IS1920PROCESS(elk,clr.enb)VARIABLEQ:STD^OGICJ.^CTOR(3DOWNTO0);3EGIN一一IFclr=,l,THENQ:=r,0000r,;ELSIFen^'l*THENIFelk'EVENTANDclk^'l*THENQ:=Q+1;ENDIF;ENDIF;cc*Jt<=Q;ENDPROCESS;ENDARCHITECTUREone;(2)仿真波形为0~15。实验内容(6)(1)原理
3、图:(2)仿真波形CEKrumruTnjmjmrLrumrmnRrwuimuwMlEHRST111111111111IIlllllIlliIIIIllillllllll谆3SDATA参8SDOUT2.设计7段数码显示译码器。⑴代码：LIBRARYIEEE;USEIEEE・STD_IX)G：［C_1164.ALU;□ENTITYdisplay7IS~5678Sport(I:INSTD_LOGIC_VECTOR(3DOWNTO0);O:OUTSTD_LOGIC_VECTOR(6DOWNTO0))；__ENDENTITYdisplay7;□
4、ARCHITECTUREmeOFdisplay7ISSBEGIN10HPROCESS(I)BEGIN11sCASEIIS12WHEN”0000”=>0<=,f0111111,13WHEN”0001”=>0<=,f0000110,14WHEN”0010”=>0<=,f1011011,15WHEN”0011”=>0<=,f1001111,16WHEN”0100”=>0<=,f1100110,17WHEN”0101”=>0<=,f1101101,18WHENn011Qn=>0<=,f1111101,19WHENn0111n=>
5、0<=,f0000111,20WHEN”1000”=>O<=,flllllll,21WHEN”1001”=>0<=,f1101111,22WHENn1010n=>0<=,f1110111,23WHENn1011n=>0<=,f1111100,24WHENn110Qn=>0<=,f0111001,25WHENn1101n=>0<=,f1011110,26WHENnlllQn=>0<=,f1111001,27WHENnlllln=>0<=,f1110001,28WHENOTHERS=>NULL;29ENDCASE;30E
6、NDPROCESS;31ENDARCHITECTUREme;(2)仿真波形irprx^rnrprr^nrnrnnnrnrrnnn^nr^Tn仿真结果分析：七段显示管中的七段分别对应的是0[6]〜0[0],当输入为0时，显示0(01111111),十六进制为3F;当输入为1时，显示1(0000110),十六进制为06,—次类推.实验内容3：⑴代码：1LIBRARYIEEE;2USEIEEE.STD_LOGIC_1164.ALL;3USEIEEE.STDLOGICUNSIGNED.ALL;4□ENTITYCNT4BIS5HPORT(CLK
7、,RST,ENA:INSTD_LOGIC;6OUTY:OUTSTDLOGICVECTOR(37COUT:OUTSTDLOGIC8)；9ENDENTITYCNT4B;10□ARCHITECTUREoneOFCNT4BIS11□BEGIN12HPROCESS(CLKrENAzRST)13VARIABLEQ:STD_LOGIC_VECTOR(3DOWNTO0);14BEGIN15aIFRST=,0,THENQ:="0000";16aELSIFCLK*EVENTANDCLK=111THEN17aIFENWTHEN18aIFQ=rrllllnT
8、HENCOUT<=,1,;Q:=r,0000r,;19aELSEQ:=Q+1;20ENDIF;21ENDIF;22ENDIF;23OUTY<=Q;24ENDPROCESS;25ENDARCHITECTUREone;DOW
