1、library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shuzizhong is port(clk : in std_logic; ‐‐‐时钟信号 choose,set,s1,s2:in std_logic; ‐‐‐‐12/24时制选择，设置，时设置，分设置 am,pm,spk:out std_logic; ‐‐‐‐上午，下午，报时信号 b:out std_logic_vector(6 downto 0);
2、‐‐‐‐七段数码管 cat:out std_logic_vector(5 downto 0) ‐‐‐数码管选通控制信号 ); end shuzizhong; architecture a of shuzizhong is signal hou1 : integer range 0 to 23; ‐‐‐24时制小时信号 signal hou2 : integer range 0 to 11; ‐‐‐12时制小时信号 signal min : integer range 0 to 59; ‐‐‐分信号 signal sec : in
3、teger range 0 to 59; ‐‐‐秒信号 signal temp: integer range 0 to 19; signal clk0:std_logic; ‐‐‐‐‐计时时钟信号 signal tmp:integer range 0 to 999999; signal a:std_logic_vector(1 downto 0); type str is array (0 to 5) of integer range 0 to 9; ‐‐‐定义整型数组 signal timeout : str; signal
4、count : integer range 0 to 5; begin p1:process(clk) ‐‐‐‐ 分频模块 begin if clk'event and clk='1' then if tmp= 999999 then ‐‐‐1M分频 ； tmp<=0; else tmp<=tmp+1; end if; if tmp<500000 then
5、 clk0<='0'; else clk0<='1'; end if; end if; end process p1; p2: process(clk0,choose,set,s1,s2) begin if clk0'event and clk0='1' then if set='0' then ‐‐‐‐计时模块
6、 sec<=sec+1; ‐‐‐‐秒计时 if sec=59 then sec<=0; ‐‐‐‐‐秒进位 min<=min+1; ‐‐‐‐分计时 if min=59 then min<=0; hou1<=hou1+1; ‐‐‐‐24小时进制小
7、时位计时 if hou1=23 then hou1<=0; end if; hou2<=hou2+1; ‐‐‐‐12小时进制小时位计时 if hou2=11 then hou2<=0; e
