vhdl与数字系统eda设计

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1、VHDL与数字系统EDA设计姓名：李勃学号：0800030014班级：代培生班2009年6月20日目录实验一1实验二5实验三8实验四10实验五14作业18VHDL与数字系统EDA设计李勃0800030014实验一1.用IF语句设计一个四－十六译码器；2.用CASE语句设计一个四－十六译码器；3.用GENERATE语句构造一个串行的十六进制计数器。实验目的：学会使用相关EDA软件进行VHDL代码的输入、仿真，会用VHDL实现一些简单的组合逻辑和时序逻辑。1.用IF语句设计一个四－十六译码器实验方案：接口信号的定义如下：port(A:inSTD_LOGIC;B:inSTD_LOGIC

2、;C:inSTD_LOGIC;D:inSTD_LOGIC;Y:outSTD_LOGIC_VECTOR(15downto0));enddecoder;关键部分代码：process(A,B,C,D)variablecomb:STD_LOGIC_VECTOR(3downto0);begincomb:=A&B&C&D;ifcomb="0000"thenY<="0000000000000001";elsifcomb="0001"thenY<="0000000000000010";elsifcomb="0010"thenY<="0000000000000100";elsifcomb="001

3、1"thenY<="0000000000001000";elsifcomb="0100"thenY<="0000000000010000";elsifcomb="0101"thenY<="0000000000100000";elsifcomb="0110"thenY<="0000000001000000";elsifcomb="0111"thenY<="0000000010000000";elsifcomb="1000"thenY<="0000000100000000";elsifcomb="1001"thenY<="0000001000000000";elsifcomb="10

4、10"thenY<="0000010000000000";elsifcomb="1011"thenY<="0000100000000000";elsifcomb="1100"thenY<="0001000000000000";elsifcomb="1101"thenY<="0010000000000000";elsifcomb="1110"thenY<="0100000000000000";elsifcomb="1111"thenY<="1000000000000000";18VHDL与数字系统EDA设计李勃0800030014elseY<="XXXXXXXXXXXXXXXX";

5、endif;endprocess;仿真验证：仿真软件：ActiveHDL7.12.用CASE语句设计一个四－十六译码器实验方案：接口信号的定义如下：entitydecoder2isport(A:inSTD_LOGIC_VECTOR(3downto0);Y:outSTD_LOGIC_VECTOR(15downto0));enddecoder2;关键部分代码：process(A)begincaseAiswhen"0000"=>Y<="0000000000000001";when"0001"=>Y<="0000000000000010";when"0010"=>Y<="00000000

6、00000100";when"0011"=>Y<="0000000000001000";when"0100"=>Y<="0000000000010000";when"0101"=>Y<="0000000000100000";18VHDL与数字系统EDA设计李勃0800030014when"0110"=>Y<="0000000001000000";when"0111"=>Y<="0000000010000000";when"1000"=>Y<="0000000100000000";when"1001"=>Y<="0000001000000000";when"1010"=>Y<="0

7、000010000000000";when"1011"=>Y<="0000100000000000";when"1100"=>Y<="0001000000000000";when"1101"=>Y<="0010000000000000";when"1110"=>Y<="0100000000000000";when"1111"=>Y<="1000000000000000";whenothers=>Y<="XXXXXXXXXXXXXXXX";endcase;endprocess;仿真